一种考虑动态优先级的VC调度算法

在分析VC(virtual clock)分组调度算法的优点和缺点的基础上,针对VC算法的静态优先级策略的主要缺点,即优先级只能在数据流建立初期指定,不能动态的改变,从而使得优先级的建立受到很大的限制进行了改进,提出动态优先级的策略,提出了一种考虑动态优先级的VC调度算法.阐述了设计的目标、改进措施,并给出了算法描述和软件仿真,仿真结果说明:动态优先权的应用使得数据流可以方便地根据实际情况灵活的调整自身的性能要求,从而可以更加方便地满足用户要求的变化.     

RCS-900系列保护装置与2048 kbit/s复用通道时钟的配合

在RCS-900系列保护装置采用2 048 kbit/s复用通道的推广过程中,发现打开通道的输出再定时功能,并且将保护装置的通信时钟设置为内时钟方式时,保护装置接收信号会产生滑码。针对上述现象,研究了通道输出再定时对业务频率的影响,并测试了通道输出再定时以及两侧保护装置通信发送时钟在各种模式组合下的业务传送效果。研究结果表明:通道输出再定时能把来自数字同步网的定时基准信号和业务数据信号合成在一起送给外接继电保护装置;打开通道输出再定时功能时,需将继电保护装置通信时钟设置为“从 — 从”方式;关闭通道输出再定时功能时,至少将一侧继电保护的通信时钟设置为内时钟方式。     

Development of a 4 MV Laser-Triggered Multi-Stage Switch

A 22-stage 4 MV laser-triggered multistage multi-channel switch （LTS） was designed according to the hypothesis that the well-proportioned electrical field distribution is helpful in reducing the jitter of delay. Field distribution in the switch section is regulated by a metal field regulation ring and several gradient rings. In order to reduce the jitter further, a SFB/N2 mixture is chosen as the switching medium. The generalized standard deviation of the self-breakdown voltage and the deviation of the average value from the prediction is less than 4.4% and 13% respectively. Linearity of the self-breakdown voltage is better than 0.95. Triggered by a laser pulse of 35 mJ/3 ns, the delay is about 26 ns at a working voltage of 85±3% USB （Self-breakdown Voltage）. Maximum deviation of delay is less than =t=2.5 ns. Jitter is less than 1.5 ns. The delay and jitter decrease with the increase in the working ratio （the ratio of working voltage to USB）, pressure or voltage.     

基于FPGA的任意相位时钟管理器的设计

在通信双方为同源时钟的前提下,为保证时钟在接口处把所有数据都正确采样进来,利用Altera的综合开发平台Quartus II,实现了采样时钟相位根据输入数据相位自动调整,使采样时钟能找到最佳的采样时间来采样外来数据。任意相位时钟管理器可以产生高精度动态相位的时钟信号。     

Evolutionary Analysis and Functional Identification of Clock-Associated PSEUDO-RESPONSE REGULATOR (PRRs) Genes in the Flowering Regulation of Roses

Pseudo-response regulators (PRRs) are the important genes for flowering in roses. In this work, clock PRRs were genome-wide identified using Arabidopsis protein sequences as queries, and their evolutionary analyses were deliberated intensively in Rosaceae in correspondence with angiosperms species. To draw a comparative network and flow of clock PRRs in roses, a co-expression network of flowering pathway genes was drawn using a string database, and their functional analysis was studied by silencing using VIGS and protein-to-protein interaction. We revealed that the clock PRRs were significantly expanded in Rosaceae and were divided into three major clades, i.e., PRR5/9 (clade 1), PRR3/7 (clade 2), and TOC1/PRR1 (clade 3), based on their phylogeny. Within the clades, five clock PRRs were identified in Rosa chinensis. Clock PRRs had conserved RR domain and shared similar features, suggesting the duplication occurred during evolution. Divergence analysis indicated the role of duplication events in the expansion of clock PRRs. The diverse cis elements and interaction of clock PRRs with miRNAs suggested their role in plant development. Co-expression network analysis showed that the clock PRRs from Rosa chinensis had a strong association with flowering controlling genes. Further silencing of RcPRR1b and RcPRR5 in Rosa chinensis using VIGS led to earlier flowering, confirming them as negative flowering regulators. The protein-to-protein interactions between RcPRR1a/RcPRR5 and RcCO suggested that RcPRR1a/RcPRR5 may suppress flowering by interfering with the binding of RcCO to the promoter of RcFT. Collectively, these results provided an understanding of the evolutionary profiles as well as the functional role of clock PRRs in controlling flowering in roses.     

ns2深度探索及在网络传输性能分析中的应用

为了提高网络的效能,需要不断研究新的网络协议和算法。而要在实际的网络环境中验证和测试它们会受到网络的复杂性和经济等因素的限制,而网络仿真能很好地解决这个问题。另外,在网络教学中,网络仿真也可形象展示网络协议的行为。文章首先介绍了网络仿真工具ns2的体系结构,并重点剖析了分裂对象模型的设计原理,以分析计算网络性能来说明ns2的应用以及如何扩展ns2的功能,并演示了抖动率的计算效果。     

用分量匹配法实现对高速时钟电路的动态优化

本文讨论如何设计工作在GHz频率下的VLSI芯片时钟电路.时钟树采用平衡平面布局消除时钟偏差;利用插入缓冲器对电路性能进行动态优化.最后用一个电路模拟软件对电路进行评估.和以往的工作相比较,本文实现了在频域内对时钟电路的优化,显著地提高了仿真速度.     

基于IEEE1588协议的局域网精确时钟同步研究

文章首先介绍IEEE1588时钟同步基本原理,然后搭建了在ARM11微处理器S3C6410A下采用WinCE6.0系统的测试平台。在该测试平台下,给出了时钟同步的纯软件和硬件辅助设计,硬件辅助设计中采用了半导体芯片DP83640。经过测试,纯软件设计的时钟同步精度可达次毫秒级,而硬件辅助设计的时钟同步精度可达到次微秒级。     

一种快捕获宽调节范围的锁相环

提出了一种快捕获,低抖动,宽调节范围的增益自适应锁相环的设计.在这个方案中,采用了双边触发的鉴频鉴相器(dual-edge-triggered phase frequency detector)和自调节压控振荡器(self-regulated voltage controlled oscillator)并进行了详细的分析.芯片的加工工艺是0.5μm 1P3M CMOS标准数字逻辑工艺.测试结果表明输入频率变化在捕获范围的37%时,捕获时间为150ns;输出频率为640MHz时,均方根抖动为39ps.