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71.
In this paper, a 16-bit 1MSPS foreground calibration successive approximation register analog-to-digital converter (SAR ADC) is developed by the CMOS 0.25 μm process. An on-chip all-digital foreground weights calibration technique integrating self-calibration weight measurement with PN port auto-balance technique is designed to improve the performance and lower the costs of the developed SAR ADC. The SAR ADC has a chip area of 2.7 × 2.4 mm2, and consumes only 100 μW at the 2.5 V supply voltage with 100 KSPS. The INL and DNL are both less than 0.5 LSB. 相似文献
72.
This paper describes the design of a high performance Si-Gate CMOS LSI circuit for an Adaptive Delta Modulation System (ADM). The circuit design is based on 4 μ design rules. The size of the die is approximately 25 mm2 and the circuit operates synchronously under the control of an 8 MHz two phase non-overlapping clock. A fault tolerant scheme is used at the comparator section for reliability improvement purposes. The adaptation logic of the system is based on the algorithm introduced in [2] where a rigorous proof is provided for showing the optimality of the algorithm in terms of performance. This paper demonstrates the feasibility of implementing this algorithm with a single chip adaptive delta modulator. 相似文献
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76.
A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the charge error induced by PVT variations is proposed.With the proposed BCT,the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably.The prototype ADC based on the proposed BCT is realized in a 0.18μm CMOS process,with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm~2.The prototype ADC achieves a spurious free dynamic range(SFDR) of 67.7 dB,a signal-to-noise ratio(SNDR) of 57.3 dB,and an effective number of bits(ENOB) of 9.0 for a 3.79 MHz input at full sampling rate.The measured differential nonlinearity(DNL) and integral nonlinearity (INL) are +0.5/-0.3 LSB and +0.7/-0.55 LSB,respectively. 相似文献
77.
采用截止频率fT为170 GHz的InP-DHBT工艺,我们设计并制作了一个超高速主从电压比较器。整个芯片的面积(包括焊盘)是0.75?1.04 mm2,在-4V的单电源电压下消耗的功耗是440mW(不包括时钟产生部分)。整个芯片包含了77个InP DHBTs。比较器的尼奎斯特测试到了20GHz,输入灵敏度在10 GHz采样率的时候是6mV,在20 GHz的时候是16 mV。据我们所知,这在国内还是第一次在单片上集成超过70个InP DHBTs的电路,也是目前国内具有最高采样率的比较器。 相似文献
78.
《Measurement》2014
A simple method for reducing the uncertainty of reference standards has been proposed for gauge block comparator calibration. Errors due to the reference value of the length difference for mechanical comparator evaluation can be reduced by using the average of two reference values. Two reference values of length difference are obtained by the appropriate combination of three gauge blocks. Errors caused by reference gauges are canceled and averaged. An error reduction effect was successfully demonstrated using an actual mechanical comparator. 相似文献
79.
The measurement of freon (mainly R134a) leaks is an important task of metrology. The paper deals with the study of the possibilities of improvement of gravimetric traceability method for the permeation secondary standards of atmospheric freon leaks. Their leak rates are different under atmospheric and vacuum conditions; only the first one is interesting for practical use. Moreover, the desirable steady state after changing the conditions is achieved only after certain relaxation time. This complicates the correction of the buoyancy influence, which causes the uncertainty increase. The leak rates of a typical secondary standard of this kind under atmospheric and vacuum conditions are compared, the needed relaxation times searched and some possibilities of further improvement discussed. 相似文献
80.