IEEE-Compliant IDCT on FPGA-Augmented TriMedia

This paper presents a TriMedia processor extended with an IDCT reconfigurable design, and assesses the performance gain such an extension has when performing MPEG-2 decoding. We first propose the skeleton of an extension of the TriMedia architecture, which consists of a Field-Programmable Gate Array (FPGA)-based Reconfigurable Functional Unit (RFU), a Configuration Unit managing the reconfiguration of the RFU, and their associated instructions. Then, we address the computation of the 8 × 8 (2-D) IDCT on such extended TriMedia and propose a scheme to implement the 1-D IDCT operation on the RFU. When mapped on an ACEX EP1K100 FPGA from Altera, the proposed 1-D IDCT exhibits a latency of 16 and a recovery of 2 TriMedia@200 MHz cycles, and occupies 45% of the logic cells of the device. By configuring the 1-D IDCT on the RFU at application launch-time, the IEEE-compliant 2-D IDCT can be computed with the throughput of 1/32 IDCT/cycle. This figure translates to an improvement over the standard TriMedia of more than 40% in terms of computing time when 2-D IDCT is carried out in the framework of MPEG-2 decoding. Finally, the proposed reconfigurable IDCT is compared to a number of existing designs.Mihai Sima was born in Bucharest, Romania. He received the MS degree in Electrical Engineering from Politehnica University of Bucharest, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He had been with the Microelectronics Company in Bucharest for 3 years, where he was involved in instrumentation electronics for integrated circuit testing. Subsequently, he joined the Telecommunications Department of Politehnica University of Bucharest, where he had been involved in digital signal processing and speech recognition for 6 years. More recently, he had been with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, where he worked on reconfigurable architectures for mediaprocessing domain. He is currently an assistant professor with the Department of Electrical and Computer Engineering, University of Victoria, B.C., Canada. His research interests include computer architecture, reconfigurable computing, embedded systems, digital signal processing, and speech recognition.Sorin D. Coofan was born in Mizil, Romania. He received the MS degree in Computer Science from the Politehnica University of Bucharest, Romania, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He had worked with the Research & Development Institute for Electronic Components (ICCE) in Bucharest for a decade, being involved in structured design of digital systems, design rule checking of ICs layout, logic and mixed-mode simulation of electronic circuits, testability analysis, and image processing. He is currently an associate professor with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, The Netherlands. His research interests include computer arithmetic, parallel architectures, embedded systems, reconfigurable computing, nano-electronics, neural networks, computational geometry, and computer aided design.Jos T.J. van Eijndhoven was born in Roosendaal, The Netherlands. He studied Electrical Engineering at the Eindhoven University of Technology, The Netherlands, obtaining the M.Sc. and Ph.D. degrees in 1981 and 1984, respectively, for a work on piecewise linear circuit simulation. Then, he became a senior research member in the design automation group of the Eindhoven University of Technology. In 1986 he spent a sabbatical period at the IBM Thomas J. Watson Research Laboratory, Yorktown Heights, New York, for research on high level synthesis. In 1998 he joined Philips Research Laboratories in Eindhoven, The Netherlands, to work on the architectural design of programmable multimedia hardware and the associated mapping of media processing applications.Stamatis Vassiliadis was born in Manolates, Samos, Greece. He is a professor with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, The Netherlands. He has also served in the faculties of Cornell University, Ithaca, NY, and the State University of New York (S.U.N.Y.), Binghamton, NY.He hadworked for a decade with IBM in the AdvancedWorkstations and Systems laboratory in Austin TX, the Mid-Hudson Valley Laboratory in Poughkeepsie, NY, and the Glendale Laboratory in Endicott, NY. In IBM he was involved in a number of projects regarding computer design, organizations, and architectures and the leadership to advanced research projects. A number of his design and implementation proposals have been implemented in commerciallyavailable systems and processors including the IBM 9370 model 60 computer system, the IBM POWER II, the IBM AS/400 Models 400, 500, and 510, Server Models 40S and 50S, the IBM AS/400 Advanced 36, and the IBM S/390 G4 and G5 computer systems. For his work, he received numerous awards including 23 levels of Publication Achievement Awards, 15 levels of Invention Achievement Awards and an Outstanding Innovation Award for Engineering/Scientific Hardware Design in 1989. In 1990 he has been awarded the highest number of USA patents in IBM, six of his 70 USA patents being rated with the highest patent ranking in IBM.Kees A. Vissers graduated the Delft University of Technology, receiving his M.Sc. in 1980. He started directly with Philips Research Laboratories in Eindhoven where he was involved in highlevel simulation and high-level synthesis. He had been heading the research on hardware/software co-design and system level design for many years, and had a significant contribution to the TriMedia VLIW processor. From 1987 till 1988 he was a visiting researcher at Carnegie Mellon University, Pittsburgh, Pennsylvania, with the group of Don Thomas. He is currently a Research Fellow with University of California at Berkeley, Department of Electrical Engineering and Computer Sciences. His research interests include video processing, embedded media processing systems, and reconfigurable computing.     

Modular Fault Diagnosis Based on Discrete Event Systems

An awareness of failure type and location is an indispensable requirement for the establishment of adequate recovery strategies and the maintenance of Factory Automation and Process Control systems.The failure diagnosis methodology presented in this paper is based on Discrete Event Systems models and in the diagnoser concept, which enable the off-line and on-line analysis of systems failures. We present an approach for models and associated diagnosers based on a modular decomposition of the global system, with the aim of avoiding problems of exponential explosion in the number of states and computational complexity of the diagnosis process.     

On Topological Watersheds

In this paper, we investigate topological watersheds (Couprie and Bertrand, 1997). One of our main results is a necessary and sufficient condition for a map G to be a watershed of a map F, this condition is based on a notion of extension. A consequence of the theorem is that there exists a (greedy) polynomial time algorithm to decide whether a map G is a watershed of a map F or not. We introduce a notion of separation between two points of an image which leads to a second necessary and sufficient condition. We also show that, given an arbitrary total order on the minima of a map, it is possible to define a notion of degree of separation of a minimum relative to this order. This leads to a third necessary and sufficient condition for a map G to be a watershed of a map F. At last we derive, from our framework, a new definition for the dynamics of a minimum.Gilles Bertrand received his Ingénieurs degree from the École Centrale des Arts et Manufactures in 1976. Until 1983 he was with the Thomson-CSF company, where he designed image processing systems for aeronautical applications. He received his Ph.D. from the École Centrale in 1986. He is currently teaching and doing research with the Laboratoire Algorithmique et Architecture des Systémes Informatiques, ESIEE, Paris, and with the Institut Gaspard Monge, Université de Marne-la-Vallée. His research interests are image analysis, discrete topology and mathematical morphology.     

An Equivalent CTL Formulation for Condition Sequences

A condition system is a form of Petri net that interacts with other condition systems and the environment via state-based signals called conditions. The condition language framework has been used in previous papers to characterize the input/output behavior of such interacting systems, as well as to specify desired control behavior among other things. In this paper, we show that condition sequences (the specification) and condition systems (the model of the system) have an equivalent structure in the computation tree logic (CTL) framework. The primary goals of this work are to be able to utilize existing tools for program verification for our systems, and to make our work more accessible to the temporal logic community.     

High-Order Consistency in Valued Constraint Satisfaction

k-consistency operations in constraint satisfaction problems (CSPs) render constraints more explicit by solving size-k subproblems and projecting the information thus obtained down to low-order constraints. We generalise this notion of k-consistency to valued constraint satisfaction problems (VCSPs) and show that it can be established in polynomial time when penalties lie in a discrete valuation structure.A generic definition of consistency is given which can be tailored to particular applications. As an example, a version of high-order consistency (face consistency) is presented which can be established in low-order polynomial time given certain restrictions on the valuation structure and the form of the constraint graph.     

Use and evaluation of discrete test information in decision making.

Elementary decision theory is applied to the problems of evaluating discrete tests or test items used to classify people into several categories, and choosing which of several treatments is best for persons falling within each response category. The technique explicitly considers the base rates of various criterion groups and the relative seriousness of different types of errors of classification, as well as the proportion of each criterion group falling in each response category. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

广义2-D离散系统FMI模型的响应公式及局部能达性

本文讨论了广义２－Ｄ离散系统ＦＭＩ模型，给出了该模型的响应公式，并讨论了该模型的局部能达性。     

基于EDEM的翻板冷却器布料器布料效果的离散元仿真优化

翻板冷却器是一种采用逆流冷却原理的立式冷却设备。为解决翻板冷却器布料不均的问题,更好地适应多形态、多物状的物料,基于EDEM软件,针对以大豆颗粒为代表的颗粒料和以大豆低温粕为代表的粕粉料,对翻板冷却器布料器的布料情况进行了离散元仿真。通过中心组合试验回归分析的方法,以颗粒分布离散率为响应值,对撒料盘与铅锤面的倾斜夹角(简称“撒料倾角”)和转轴转速进行了优化,并将优化结果应用于检疫性大豆灭活工艺冷却工段的翻板冷却器布料器。结果表明：物料类型为以大豆颗粒为代表的颗粒料时,撒料倾角为53.59°、转轴转速为45.91 r/min时布料效果最优,颗粒分布离散率为2.44%;物料类型为以大豆低温粕为代表的粕粉料时,撒料倾角为49.02°、转轴转速为46.45 r/min时布料效果最优,颗粒分布离散率为2.99%。实际工程应用结果表明,大豆颗粒布料总体均匀,冷却情况较好。综上,基于EDEM对翻板冷却器布料器的布料效果进行优化具有可行性和有效性。     

Hybrid Level of Detail Algorithm for Real-Time Rendering of Large-Scale Terrain

Real-ti me rendering of terrain model is one of themost difficult tasks of computer graphics,especiallywhen the scale of a terrain model is very large.LODis ani mportant techniquetoresolvethis problem.Ac-cording to the evolution,there are two kinds ofLOD:…