Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

This study investigates the effects of oxide traps induced by SOI of various thicknesses (T_SOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner T_SOI devices have a smaller net remaining stress in gate oxide film than thicker T_SOI devices, and thus possess a smaller bulk oxide trap (N_BOT) and reveal a superior gate oxide reliability. On the other hand, the thicker T_SOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker T_SOI device has a higher bulk oxide trap (N_BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T_SOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.     

InP晶片位错密度分布测量

采用国际通用的方法,测定了不同类型的用高压LEC法生长的InP单晶样品的整片位错分布,直观显示位错密度在晶片上的分布情况,分析了EPD分布结果和原因,说明单晶生长工艺和掺杂剂等因素对其产生影响.从数值看,一般掺S的材料位错密度较低,随着掺杂浓度的增加位错密度明显降低,晶片的均匀性也越好.掺Fe的材料位错密度一般,但随着...     

光纤布喇格光栅铅酸蓄电池容量检测传感器研究

根据光纤布喇格光栅(FBG)折射率传感原理,提出使用腐蚀的FBG制作成的相移光栅折射率传感器测量铅酸蓄电池剩余容量的方案.将电解液的折射率变化与电解液浓度测量联系起来,而电解液浓度又与铅酸蓄电池容量有一一对应的函数关系,从而通过测量铅酸蓄电池电解液浓度就可知蓄电池的容量状态.此法能很好地实现铅酸蓄电池容量的在线测量.该传感器具有测量准确,反应灵敏,使用寿命长等优点.     

Influence of double application technique on the bonding effectiveness of self‐etch adhesive systems

Aim: To evaluate and compare the effect of double‐application of single‐step self‐etch adhesives using microleakage study and to analyze the dentin–adhesive interfacial micromorphology. Methods: In total, 72 extracted human premolars were divided into three groups for different self‐etch adhesives (G Bond, GC [GB], Optibond, Kerr [OB], and Xeno V Plus, Dentsply [XV]). Class V cavities were prepared. Each group was further divided into two subgroups (n = 10) according to the placement technique of the adhesive, using the single‐application [subgroup (a)] or double‐application method [subgroup (b)]. Resin composite (Z 250, 3M ESPE, St. Paul, MN) was used to restore the cavities and light cured for 40 s. Twenty samples from each group were subjected to microleakage study. Two samples from both the subgroups of the three adhesives were used for scanning electron microscopic examination of the resin–dentin interfacial ultrastructure. Dye leakage scores were subjected to statistical analysis using Kruskal–Wallis and Mann–Whitney U‐tests at significance level of P < 0.05. Results: GB depicted significantly more microleakage which was significantly greater than OB and XV. The double application led to significant decrease in microleakage of GB with no significant effect on the microleakage scores of other two all‐in‐one adhesives, that is OB and XV. Conclusion: Double application of all‐in‐one self‐etch adhesives improves the marginal sealing ability in dentin although it appears to be product dependent. Microsc. Res. Tech. 78:489–494, 2015. © 2015 Wiley Periodicals, Inc.     

组合结构的牺牲层释放腐蚀修正模型

Eaton等人曾给出了HF溶液腐蚀SiO2牺牲层的释放腐蚀模型,然而实验中发现该模型并不能较好地符合实验数据.经分析发现该模型中扩散系数和反应速率常数不能如实反映温度的变化,而且实验中观察到腐蚀前端形状并不总是平面.通过对模型中这些因素的修正,建立起修正模型,证实修正模型比Eaton给出的模型更符合实验结果     

微型双岛硅膜制作中的削角补偿方法研究

针对微型双岛硅膜制作中的凸角削角腐蚀问题，提出了一种新的削角补偿方法一“两端矩形补偿法”，并在感压膜尺寸仅为０．７２ｍｍ×１ｍｍ的双岛硅膜制作中获得成功。     

Silicon Nanowires Driving Miniaturization of Microelectromechanical Systems Physical Sensors: A Review

The miniaturization of microelectromechanical systems (MEMS) physical sensors is driven by global connectivity needs and is closely linked to emerging digital technologies and the Internet of Things. Strong technical advantages of miniaturization such as improved sensitivity, functionality, and power consumption are accompanied by significant economic benefits due to semiconductor manufacturing. Hence, the trend to produce smaller sensors and their driving force resemble very much those of the miniaturization of integrated circuits (ICs) as described by Moore's law. In this respect, with its IC-, and MEMS-compatibility, and scalability, the silicon nanowire is frequently employed in frontier research as the sensor building block replacing conventional sensors. The integration of the silicon nanowire with MEMS has thus generated a multiscale hybrid architecture, where the silicon nanowire serves as the piezoresistive transducer and MEMS provide an interface with external forces, such as inertial or magnetic. This approach has been reported for almost all physical sensor types over the last decade. These sensors are reviewed here with detailed classification. In each case, associated technological challenges and comparisons with conventional counterparts are provided. Future directions and opportunities are highlighted.     

硅微透镜阵列的制备工艺

开发了一种和MEMS工艺兼容的基于硅微加工技术的简易硅微透镜阵列制造技术。利用光刻胶热熔法和等离子体刻蚀法相结合的方法,实现了在硅晶圆上制作不同尺寸的硅微透镜阵列的工艺过程。实验中,对透镜制作过程中的热熔工艺、刻蚀工艺进行了深入的研究。最终确定了最优的工艺参数,制备了孔径在20~90μm、表面质量高的硅微透镜阵列。     

A fun and educative way for students to learn the nanofabrication through hands-on processing: Microletters

A 12-h hands-on processing protocol for a nanofabrication lab module is developed with the intention of teaching high school to college undergraduate students major fabrication techniques. The nanofabrication techniques employed are thin film deposition, direct-write lithography, conventional UV lithography with a mask aligner, etch, dicing, and characterization. The lab module protocol concludes with the student fabricating their own microletter silicon chip with a personalized message with letters and images through hands-on processing. For academic discussion, the light interference in thin film, deposition and etch rate, and etch selectivity are studied during the lab module.