Fabrication of a planar water gated organic field effect transistor using a hydrophilic polythiophene for improved digital inverter performance

A planar water gated OFET (WG-OFET) structure is fabricated by patterning gate, source and drain electrodes on the same plane at the same time. Transistor output characteristics of this novel structure employing commercial regioregular poly(3-hexylthiophene) (rr-P3HT) as polymer semiconductor and deionized (DI) water as gate dielectric show successful field effect transistor operation with an on–off current ratio of 43 A/A and transconductance of 2.5 μA/V. These output characteristics are improved using P3HT functionalized with poly(ethylene glycol) (PEG) (P3HT-co-P3PEGT), which is more hydrophilic, leading to on–off ratio of 130 A/A and transconductance of 3.9 μA/V. Utilization of 100 mM NaCl solution instead of DI water significantly increases the on–off ratio to 141 A/A and transconductance to 7.17 μA/V for commercial P3HT and to 217 A/A and to 11.9 μA/V for P3HT-co-P3PEGT. Finally, transistors with improved transconductances are used to build digital inverters with improved characteristics. Gain of the inverters employing P3HT and P3HT-co-P3PEGT are measured as 2.9 V/V and 10.3 V/V, respectively, with 100 mM NaCl solution.     

Detailed analysis and contact properties of low-voltage organic thin-film transistors based on dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) and its didecyl and diphenyl derivatives

Low-voltage organic thin-film transistors (TFTs) based on four different small-molecule semiconductors (pentacene, DNTT (dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene), C₁₀-DNTT and DPh-DNTT) were fabricated, and a detailed comparison of the semiconductor thin-film morphology, of the current-voltage characteristics of transistors with channel lengths ranging from 100 to 1 μm, and of the contact resistances is provided. The three thienoacene derivatives DNTT, C₁₀-DNTT and DPh-DNTT all have significantly larger charge-carrier mobilities and smaller contact resistances than pentacene. In terms of the intrinsic channel mobility (determined using the transmission line method), C₁₀-DNTT and DPh-DNTT perform quite similarly and notably better than DNTT, suggesting that the decyl substituents in C₁₀-DNTT and the phenyl substituents in DPh-DNTT provide a similar level of enhancement of the charge-transport characteristics over DNTT. However, the DPh-DNTT TFTs have a substantially smaller contact resistance than both the DNTT and the C₁₀-DNTT TFTs, resulting in notably larger effective mobilities, especially in transistors with very small channel lengths. For DPh-DNTT TFTs with a channel length of 1 μm, an effective mobility of 0.68 cm²/V was determined, together with an on/off ratio of 10⁸ and a subthreshold swing of 100 mV/decade.     

A course on thin‐film transistor circuit design for modern displays

A new subject‐specific course on thin‐film transistor (TFT) circuit design is introduced, covering related knowledge of display technologies, TFT device physics, processing, characterization, modeling and circuit design. A design project is required for students to deepen the understanding even more and get hands‐on design experience. This course can be an intense 1‐week course to offer a full training of design engineers in an organized way to meet the ever‐increasing needs in display industry for TFT circuit design specialists. It can also be organized in one semester for electrical engineering Master's and Ph.D. students.     

Solution-processed ytterbium oxide dielectrics for low-voltage thin-film transistors and inverters

High permittivity (high k) metal-oxide thin films fabricated via solution processes have recently received much attention for the construction of low-operating voltage and high-performance thin-film transistors (TFTs). In this report, amorphous ytterbium oxide (Yb₂O₃) thin films were fabricated by spin coating and their applications in TFTs were explored. The physical properties of the solution-processed Yb₂O₃ thin films processed at different annealing temperatures were systematically investigated using various characterization techniques. To explore the feasibility of the Yb₂O₃ thin films as gate dielectrics for oxide TFTs, In₂O₃ TFTs based on Yb₂O₃ dielectrics were integrated. All the devices could be operated at 3 V, which is critical for the applications in portable, battery-driven, and low-power electronic devices. The optimized In₂O₃/Yb₂O₃ TFT exhibits high electrical performances, including field-effect mobility of 4.98 cm²/V s, on/off current ratio of ~ 10⁶, turn-on voltage around 0 V, and subthreshold swing of 70 mV/decade, respectively. To demonstrate the potential of In₂O₃/Yb₂O₃ TFT toward more complex logic application, the unipolar inverter was further constructed.     

Accounting for variability in the design of circuits with organic thin-film transistors

We experimentally verify that the methodology to account for local parameter variations and transistor mismatch known in Si CMOS technologies can be transposed to organic thin-film transistor technologies, and we present a design case that makes use of design for variability. Transistor parameter variation decreases with the square root of the transistor footprint. As a consequence, Monte Carlo simulations which take this effect into account can be executed to better predict the final circuit yield. The design case in this work is an 8-bit, organic RFID transponder chip. The yield prediction by simulations corresponds to the finally observed circuit yield.     

Carboxylic acid mediated self-assembly of small molecules for organic thin film transistors

A p-type small molecule bearing dicarboxylic acid functional group (–COOH) is synthesized and evaluated for field-effect transistor properties. We discover and report for the first time, that the –COOH groups assist in the passivation of surface traps on the dielectric layer and simultaneously facilitate the self-assembly of the molecules via inter-molecular hydrogen bonding resulting in crystalline active channels. A 9-fold decrease in the threshold voltage was observed for the transistors made using the –COOH functionalized molecule, QT-DA, compared to its ester analogue, QT-ES, providing an evidence of surface passivation. This resulted in an increase in the hole mobility of QT-DA by up to 2 orders of magnitude. It was shown that QT-DA adopts a vertical alignment with respect to the substrate due to preferential interaction between the –COOH groups and the SiO₂ surfaces.     

雪崩击穿条件下4.5kV IGBT器件的背面优化研究

The static avalanche breakdown behavior of 4.5 kV high-voltage IGBT is studied by theory analysis and experiment. The avalanche breakdown behaviors of the 4.5 kV IGBTs with different backside structures are investigated and compared by using the curve tracer. The results show that the snap back behavior of the breakdown waveform is related to the bipolar PNP gain, which leads to the deterioration of the breakdown voltage. There are two ways to optimize the backside structure, one is increasing the implant dose of the N C buffer layer, the other is decreasing the implant dose of the P C collector layer. It is found that the optimized structure is effective in suppressing the snap back behavior and improving the breakdown characteristic of high voltage IGBT.     

The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor

The analog performance of gate misaligned dual material double gate junctionless transistor is demonstrated for the first time. The cases considered are where misalignment occurs towards source side and towards drain side. The analog performance parameters analyzed are: transconductance, output conductance, intrinsic gain and cut-off frequency. These figures of merits (FOMs) are compared with a dual material double gate inversion mode transistor under same gate misalignment condition. The impacts of different length of control gate (L₁) for a given gate length (L) are also studied and the optimum lengths L₁ under misalignment condition to have better analog FOMs and high tolerance to misalignment are presented.     

Automating the sizing of transistors in CMOS gates for low‐power and high‐noise margin operation

This paper presents an automatic method for sizing the transistors in CMOS gates. The method utilizes a feedback control system to efficiently optimize the transistor sizes in small and large fan‐in gates, with the primary goal of enhancing noise robustness (as characterized by the static noise margin). The gates retain their robustness under threshold‐voltage variations over a range of supply voltages. The optimized gates not only expend reduced power and energy, but also take up less area than the conventional ones. These multi‐faceted gains, however, do incur some performance loss. Copyright © 2014 John Wiley & Sons, Ltd.