爆炸磁频率发生器电感特性分析

从爆炸磁频率发生器的等效电路原理分析,研究电感的变化规律对发生器工作电流时间特性及频谱特性的影响及比较,结果表明：电感减小率以先快后慢的形式变化时,能提高发生器抗击穿的能力和工作频率,接着从实际模型出发,对有电枢存在时的电感计算进行修正,提高了发生器电感计算的精确度,最后,通过实验的方法验证了爆炸磁频率发生器产生脉冲辐射的可能性。     

超短波频段脉冲产生器的设计及硬件实现

从频域角度考虑了产生脉冲的方法,通过滤波器对单位冲激响应进行频谱整形,达到将脉冲控制在固定频谱范围内的目的。通过ADS和Protel对电路进行仿真设计和硬件实现。测试结果表明,该脉冲产生器输出结果达到了预期要求,实测结果与仿真结果吻合得很好。最终输出脉冲峰峰值为1．17V,拖尾抑制为-12dB,具有良好的对称性,频谱基本控制在30～40MHz之间。     

信号发生器自动检定系统

信号发生器自动检定系统通过系统配置、硬件设计、系统及测量软件的编制和调试、误差分析与处理,实现了频率达到26．5GHz射频、微波合成信号发生器性能的全自动检定。单次连接可完成频率、功率、调制、频谱纯度、失真等26个参数的全部自动检定,并兼容手动、半自动、全自动的状态;已完成的被检信号发生器的型号有四十余种,且系统可以实时自动添加;系统的标准仪器配置设计结构开放,可方便替换;系统运行高速、准确、可靠。系统良好的兼容性、适应性和实用性。使系统具有较强的推广应用价值。该信号发生器自动检定系统可广泛应用于计量技术机构的信号发生器的自动检定。该系统的建立是计量检定工作的发展方向,同时对射频、微波仪器实现计量检定的自动化有着普遍的指导意义。     

Comparative Study of 10-MW High-Temperature Superconductor Wind Generator with Overlapped Field Coil Arrangement

The electromagnetic characteristics and iron loss of a high-temperature superconductor wind generator (HWG) equipped with an overlapped field coil arrangement (OFCA) are studied by comparing with the one equipped with the conventional field coil arrangement (CFCA). Through a quantitative analysis, it was found that HWG with OFCA exhibits better electromagnetic characteristics than HWG with CFCA and can reduce the iron loss by eliminating the magnetic flux sag caused by the adjacent field coil sides with the same current flow direction. In addition, the OFCA topology can further reduce the volume of the wind generator.     

电子束重复增量扫描生成三维结构的研究

针对三维曝光图形的结构特点,结合自行设计的图形发生器,提出了电子束重复增量扫描方式及曝光剂量与刻蚀深度关系和灵敏度的计算方法.根据计算得到的剂量关系,按照重复增量扫描方式,在SDS-3电子束曝光机上进行了曝光实验,显影后得到了轮廓清晰的梯锥和圆锥的三维结构.因此,重复增量扫描方式可以用于三维结构的加工,并且关于曝光剂量与刻蚀深度关系和灵敏度的计算可以为其提供符合实际曝光的参数.     

A random sequence generator based on chaotic circuits

In this paper, a random sequence generator based on chaotic circuits is presented. Fundamental principle and experimental circuit have been carried out in case of Chua's circuit. The statistical results are in good agreement with probability characteristics of random sequence.     

Data Randomization Scheme for Endurance Enhancement and Interference Mitigation of Multilevel Flash Memory Devices

In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply‐scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on‐chip pseudorandom generator composed of an address‐based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x‐nm and 4x‐nm NAND flash memory devices illustrate the effectiveness of our scheme. The results show that the error rate is reduced up to 86% compared to that of a conventional cycling scheme. Accordingly, the endurance phenomenon can be mitigated through analysis of interference that causes tech shrinkage.     

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.     

高压发电机组在邮电系统应用的可行性探讨

结合国外通信部门高压发电机组的使用民政部及国内通信发展的现状,探讨高压发电机组作为备用电源在国内大的通信局（站）使用的可行性,并对由此而构成的供电系统类型进行分析。     

低功耗输出脉冲幅度和频谱可调的超宽带发送机设计

A 3-5 GHz low power BPSK modulated impulse radio UWB transmitter is implemented in 0.13μm CMOS technology. In this design the amplitude and spectrum of the output impulse are both tunable to solve the special problem in IR-UWB, where it is difficult to control the spectrum. Measurement results indicate that, by changing the control bits in the gain control circuit and differential circuit, the 3-step peak-to-peak voltage amplitudes are 240, 170 and 115 mV and the center frequency of the impulse can be tuned from 3.2 to 4.1 GHz. A power controlled output buffer is designed to drive the antenna. The total power consumption is only 4.44 mW when transmitting a baseband signal of 100 MHz. The chip area is 1.2 × 1.4 mm^2.