基于小波分析的滤波方法及其硬件实现

传统的滤波方法是基于Ｆｏｕｒｉｅｒ分析理论，根据信号在Ｆｏｕｒｉｅｒ频域的特性设计滤波器，但这类滤波方法没有时间分辨率，有一定的局限性。近年来，一种称为小波分析的信号处理理论逐渐得到了人们的重视，因其具有时间—频率分辨率而倍受人们的青睐。本文结合小波分析理论，研究利用小波分析进行时—频域滤波的方法，并介绍其硬件实现方法。最后用数值模拟对这种方法进行了验证。     

A Simple CMOS-Based Membership Function Circuit

In this study, design and analysis of a voltage-input current-output simple CMOS-based Membership Function Circuit (MFC) is presented. The proposed MFC is based on simple OTA structure and current-mode maximum circuits. This MFC implements basic four membership functions (trapezoidal, triangle, Z-shape and S-shape). The characteristics (width, height, slope and position) of the implemented membership functions are easily adjustable and it is suitable for current-mode fuzzy hardware. While the circuit's membership function characteristics have been confirmed by PSPICE-DC simulations, the circuit's transient response has been analyzed applying up to 10 MHz input signals in continuous time by PSPICE Transient simulations.     

计算机三维动画对硬、软件的要求及创作过程

通过对国内外计算机三维动画创作技术应用的比较 ,介绍计算机硬件 (图形显示卡、图形工作站等 )的性能和工作方式以及应用软件 (3DSMAX、MAYA、SOFTIMGE、HUNIDE等 )的发展和三维动画的创作过程     

酸轧联机项目的过程数据采集及分析系统

分析了IBA公司的过程数据采集和分析系统在武钢冷轧厂酸洗-五机架轧机联机改造项目上的应用,说明了该系统的硬件配置,软件以及通讯等。     

System-Level Synthesis Using Evolutionary Algorithms

In this paper, we consider system-level synthesis as the problem of optimally mapping a task-level specification onto a heterogeneous hardware/software architecture. This problem requires (1) the selection of the architecture (allocation) including general purpose and dedicated processors, ASICs, busses and memories, (2) the mapping of the specification onto the selected architecture in space (binding) and time (scheduling), and (3) the design space exploration with the goal to find a set of implementations that satisfy a number of constraints on cost and performance. Existing methodologies often consider a fixed architecture, perform the binding only, do not reflect the tight interdependency between binding and scheduling, do not consider communication (tasks and resources), or require long run-times preventing design space exploration, or yield only one implementation with optimal cost. Here, a model is introduced that handles all mentioned requirements and allows the task of system-synthesis to be specified as an optimization problem. The application and adaptation of an Evolutionary Algorithm to solve the tasks of optimization and design space exploration is described.     

基于IDE接口的无限容量MP3设计技术

目前便携式MP3播放器一般采用非易失性存储芯片作存储器，容量小、单位成本高，且不适应长时间播放。针对上述缺点，用STC89C58RD＋单片机作为微处理器、IDE接口硬盘作为MP3的存储器，外围连接STA013解码芯片和CS4334数／模转换芯片就构成了IDE接口无限容量的MP3播放器。该MP3播放器的信息输出和人机界面采用LCD液晶显示屏，操作时显示操作提示信息，播放时显示歌曲名；红外遥控器操作可快速浏览歌曲名，实现查找、播放、停止等操作，他具有操作方便、数据解码速度快、播放效果好、播放时间长等特点，非常适应于超市、休闲广场、家庭娱乐等场合使用。文章对IDE硬盘接口原理、与单片机连接方法、解码电路和D／A转换电路的设计以及软件的设计进行了阐述。     

Processor Enhancements for Media Streaming Applications

The development of more processing demanding applications on the Internet (video broadcasting) on one hand and the popularity of recent devices at the user level (digital cameras, wireless videophones, ...) on the other hand introduce challenges at several levels. Today, such devices present processing capabilities and bandwidth settings that are inefficient to manage scalable QoS requirements in a typical media delivery framework. In this paper, we present an impact study of such a scalable data representation optimized for QoS (Matching Pursuit 3D algorithms) on processor architectures to achieve the best performance and power efficiency. A review of state of the art techniques for processor architecture enhancement let us expect promising opportunities from the latest developments in the reconfigurable computing research field. We present here the first design steps of an efficient reconfigurable coprocessor especially designed to cope with future video delivery and multimedia processing requirements. Architecture perspectives are proposed with respect to low development cost constraints, backward compatibilty and easy coprocessor usage using an original strategy based on a hardware/software codesign methodology.Sebastien Bilavarn received the M.S. degree from Rennes University (France) in 1998 and the PhD degree in Electrical Engineering from South Brittany University in 2002. Since June 2002, he works as a post-doc fellow at Signal Processing Institute, Swiss Federal Institute of Technology (EPFL). Sebastiens research interests include design methodologies for embedded systems, reconfigurable computing and Digital Signal Processing. Currently, his work focuses on using Adaptive Computing Systems to optimise computer architectures, which is a collaboration with the Architecture Research Lab of the System Technology Labs, Intel Corporation.Eric Debes received a M.S. in Electrical and Computer Engineering from Supélec, France in 1996, a M.S. in Electrical Engineering from the Technical University Darmstadt, Germany in 1997 and a PhD in Signal Processing from the Swiss Federal Institute of Technology. Since 2001 he has been a Researcher in the Architecture Research Lab of the System Technology Labs, Intel Corporation, Santa Clara, California. Erics research interests include image and video coding and processing algorithms as well as computer architecture and parallelism. At Intel he has been working together with different processor teams and microarchitecture research groups on the definition of new media and communication features (including new SIMD and streaming instructions, multicore processors and low-power architectures) in the CPU and the chipset to provide better media application performance and end user quality of service with a given system and processor power envelope and/or energy budget. More recently Eric has been working on system-on-chip modelling, processor and system power estimation and architecture design space exploration for consumer electronics applications. He is a member of the IEEE, of the ACM and of the SPIE.Pierre Vandergheynst received the M.S. degree in physics and the Ph.D. degree in mathematical physics from the Université catholique de Louvain, Belgium, in 1995 and 1998 respectively. From 1998 to 2001, he was a Postdoctoral Researcher with the Signal Processing Laboratory, Swiss Federal Institute of Technology (EPFL), in Lausanne, Switzerland. He is now an Assistant Professor of Visual Information Processing at EPFL, where is research focuses on computer vision, data processing and mathematical tools for visual information processing. Prof. Vandergheynst is Co-Editor-in-Chief of Signal Processing and member of the IEEE.Jean-Philippe Diguet received the M.S degree and the PhD degree from Rennes University (France) in 1993 and 1996 respectively. His thesis focused on the estimation of hardware complexity and algorithmic transforms for architectural synthesis. Then he joined the IMEC in Leuven (Belgium) where he worked as a post-doc fellow on the minimization of the power consumption of memories at the system-level. From 1997 to 2002, he has been an associated professor at the South Brittany University and member of the LESTER laboratory. In 2003/04, he has initiated and created an innovating company in the domain of short range wireless communications. In 2004, he obtains a CNRS researcher position. His current work focuses on design space exploration of embedded systems, real-time scheduling in the context of hardware/software architecture configurations. Within the LESTER laboratory, he heads the “Design Trotter” team focusing on EDA methods and tools.     

计算机系统资源的安全管理

硬盘是计算机系统资源和信息的重要存储设备，通过对常见硬盘故障问题的分析和探讨，简要介绍了解决问题的方法。     

Reconfigurable Antenna for Future Wireless Communication Systems

This paper deals with the processing techniques which are known as reconfigurable antennas: these methods are foreseen to be a booster for the future high rate wireless communications, both for the benefits in terms of performance and for the capacity gains. In particular, adaptive digital signal processing can provide improved performance for the desired signal in terms of error probability or signal-to-noise ratio while the bandwidth efficiency can be increased linearly with the number of transmitting and receiving antennas. In this article, the main antenna processing techniques are reviewed and described, aiming at highlighting performance/complexity trade-offs and how they could be implemented in the future systems. The coexistence of all these different technologies in a wireless environment requires high efficiency and flexibility of the transceiver. Future transceiver implementations which are based on the Software Defined Radio technology are also reviewed and described.     

USB接口在数字超声探伤PC机外置盒中的应用

以USB接口在数字超声探伤PC机外置盒中的应用为实例，简单介绍了USB技术，并着重介绍了如何结合USB协议规范利用USB控制器PDIUSBD12来进行USB的硬件、软件设计．