Nanotwin formation and its physical properties and effect on reliability of copper interconnects

Ultra-fine grained copper with a large amount of nano-scale twin boundaries has high mechanical strength and maintains normal electrical conductivity. The combination of these properties may lead to promising applications in future Si microelectronic technology, especially as interconnect material for air-gap and free-standing copper technologies. Based on first principles calculations of total energy and in-situ stress measurements, high stress followed by stress relaxation during the Cu film deposition seems to have contributed to nanotwin formation. Nanoindentation studies have shown a larger hardness for copper with a higher nanotwin density. The effect of Cu nanotwin boundaries on grain growth was investigated by scanning electron microscopy (SEM), electron backscatter diffraction (EBSD) and transmission electron microscopy (TEM). The presence of a high density of nanotwin boundaries may improve the reliability of Cu interconnects.     

Negative capacitance independent multi-gate FinFETs and their optimisations

In order to reduce the operating voltage of FinFET and increase the flexibility of integrated circuit design, we have proposed a Negative Capacitance Independent Multi-Gate FinFET (NC-IMG-FinFET) with Ferroelectric-Metal-Insulator-Semiconductor-Insulator (FMISI) structure. Both the device and circuit analysis model of NC-IMG-FinFET are addressed, which are used to analyse the performance parameters of the device (the surface potential, internal gate voltage amplification, Sub-threshold Swing (SS), on-current and leakage) and the performance of a circuit (delay, power consumption, power delay product (PDP)). The simulation model of the NC-IMG-FinFET has been constructed by combining BSIM-IMG model with ferroelectric Landau-Khalatnikov model. The optimisations for ferroelectric film thickness of the NC-IMG-FinFETs are carried out in terms of device characteristics and circuit performances. The simulation results are consistent with the analysis results, indicating that the NC-IMG-FinFET has superior performance compared with the baseline device, in terms of smaller leakage, larger on/off current ratio and smaller SS (38.3 mV/dec at room temperature). Compared with the baseline IMG-FinFET circuits, there is large performance improvement for the NC-IMG-FinFET circuits, in terms of the power consumption and PDP.     

开路缺陷的软故障关键面积研究

从软故障的产生机制出发,研究了软故障的作用模式.为了计算软     

等效集中参数模型在空载长线路教学中的应用

在＂电气工程基础＂课程的过电压教学过程中,空载架空线路的长线电容效应是一个十分重要的概念。本文从均匀架空长线的分布参数等效模型及其端点的等效集中参数模型出发,对电容效应不同的补偿方式进行等效参数分析和讨论,同时对复杂的补偿方法进行了等效分析.本文的讨论对电气工程课程的教学和工程实践具有一定的参考价值。     

叠层片式陶瓷电感器寄生电容的提取

寄生电容是叠层片式电感器的重要参数,对电感器的Q值和谐振频率影响很大.如何准确估计寄生电容的大小成为电感器设计的一个难题.采用Ansoft Q3D软件建立了叠层片式陶瓷电感器的3D静电场有限元模型,计算了各电极间的杂散电容,然后建立电感器的等效电容网络,列出节点电压方程并求解得到寄生电容.计算结果和测量结果基本一致.瓷...     

MOS Capacitance-Voltage Characteristics Ⅱ.Sensitivity of Electronic Trapping at Dopant Impurity from Parameter Variations

Low-frequency and high-frequency Capacitance-Voltage（C-V） curves of Metal-Oxide-Semiconductor Capacitors（MOSC）,including electron and hole trapping at the dopant donor and acceptor impurities,are presented to illustrate giant trapping capacitances,from>0.01C_ox to>10C_ox.Five device and materials parameters are varied for fundamental trapping parameter characterization,and electrical and optical signal processing applications.Parameters include spatially constant concentration of the dopant-donor-impurity electron trap,N_DD,the ground state electron trapping energy level depth measured from the conduction band edge, E_C—E_D,the degeneracy of the trapped electron at the ground state,g_D,the device temperature,T,and the gate oxide thickness,x_OX.     

Simulation study of the 20 nm gate-length Ge implant-free quantum well p-MOSFET

In this paper a drift diffusion simulation study of a 20 nm gate-length implant-free quantum well germanium p-MOSFET is presented, which covers the impact of mobility, velocity saturation and density of interface states on the transistor performance. The parasitic gate capacitance was also studied. The simulations show that the 20 nm gate-length implant-free quantum-well transistor design has good electrostatic integrity and performance potential.     

去耦电容在PCB中的应用

介绍在PCB板上添加去藕电容进行EMC和信号质量的优化设计方法。详细说明在添加去耦电容时，去耦电容取值大小的计算、电容类型的选择、去耦电容的摆放、不同线路的频率和上升速度大小、线路板各层之间以及时钟的自协调频率的配合、防止共振的产生等这些应用去耦电容时关注和考虑的内容。     

电阻抗成像系统中电压控制电流源的设计

在医用电阻抗层析成像（Electrical Impedance Tomography）系统中电压控制电流源的性能十分重要,大部分报道的电压控电流源电路在低频时有较高的输出阻抗但是在高频时性能大幅减弱。通过分析生物阻抗测量系统对电压控制电流源的需求,同时回顾一些已有的电压控制电流源电路,包括双运放负反馈电路、跨导运算放大器、AD844,设计了一种基于AD8610的电压控制电流源。并通过电路实验验证了此电压控制电流源的性能,同时提出了改进方案。该电压电流源不仅频率和幅值可控、精度高,而且有较高的输出阻抗。     

发光二极管负电容与角频率的关系

利用正向交流(AC)小信号方法对发光二极管(LED)的电容-电压特性进行测量,可以观察到发光二极管中的负电容现象.提出了测量到的负电容现象是表象,不存在负电容;发光二极管p-n结的结电容在特定的正向电压范围内等效于可变电容.分析可变电容对交流小信号响应得到:特定参数的可变电容使电流的相位移相π,使得在测量中表现为负电容;得到了发光二极管负电容与角频率的关系表达式.