为调谐器设计的带自动幅度控制1.1GHz差分压控振荡器

为集成调谐器接收机芯片系统设计了一个带自动幅度控制回路的差分结构电容电感压控振荡器.通过采用pMOS管作为有源负阻使振荡器谐振回路可以直接接地电平,减小了寄生效应,扩大了频率调谐的线性及其范围.采用的自动幅度控制AAC回路具有元件少,噪声低,控制灵敏,调节容易,结构简单及设计方便的优点,并保证振荡器电路的性能最小地依赖于环境和制造工艺参数的变化.所设计的压控振荡器采用新加坡特许50GHz 0.35μm SiGe BiCMOS工艺流片,经测试在1MHz频率偏移处达到了-127.27dBc/Hz的相位噪声性能,具有宽的(990～1140MHz)和线性(调谐增益32.4MHz/V)的频率调谐曲线.整个振荡器电路在5V的供电电压下仅消耗6.6mA的电流,可以满足调谐器的应用需要.     

Nonlinear analysis, design, and implementation of a VCO in S frequency band

A VCO in S frequency band is designed by using nonlinear technique based on large signal model of semiconductor devices. The nonlinear circuit of the VCO is analyzed by a novel analytical approach of harmonic balance method as an autonomous circuit, and with fulfilling the stability condition of the network, the output specifications are determined. This proposed nonlinear approach for determining of the frequency and amplitude stability is also based on harmonic balance method. The results of the analysis are compared with those of measurements. The comparison shows good agreement between results of this analytical approach and the measurements. Zahra Ghanian was born in Tehran, Iran, in 1975. She received the B.Sc. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1998, and the M.Sc. degree from the Amirkabir University of Technology, Tehran, Iran, in 2001. Since 2000, she has been involved in several research and engineering projects at the Amirkabir University of Technology, Iran Telecommunications Research Center (ITRC) and Niroo Research Institute (NRI). Her main areas of interest are design, simulation and analysis of circuits for Microwave, Millimeter wave and Wireless applications. Abdolali Abdipour was born in Iran in 1966. He obtained his B.Sc. in Electrical Engineering from Tehran University, Tehran, Iran in 1989, and the M.Sc. in Electronics from Limoges University, Limoges, France in 1992. Then he achieved his PhD degree in Electronic Engineering from Paris XI University, Paris, France in March 1996. His research areas include wireless communication systems (RF Technology and Transceivers), RF/Microwave/mm-wave circuit and system design, E & M modeling of active devices and circuits, high frequency electronics (signal and noise), nonlinear modeling and analysis of microwave devices and circuits. He has published over 80 papers in the refereed journals and international conferences. He authored two books “Noise in Electronic Communication: Modeling, Analysis and measurement” and “Transmission Lines” (in Persian). He is currently an associate professor of Electrical Engineering Department at Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran. Ayaz Ghorbani received PG diploma, m. Phiel and PhD degrees from the university of Bradford U.K. in 1984, 1985 and 1987 respectively in the area of electrical and communication engineering. From 1987 up to now he has been teaching various courses in the department of electrical engineering at university of Amirkabir (Tehran poly technique) Tehran, Iran. In 1987 he was awarded John Robertshaw Travel Award to visit a number of research establishments in the United States of America from Bradford University, and in 1990 he was also awarded U.R.S.I. Young Scientists Award at general assembly of the URSI, Prague, Czech Republic. In 2004 he was in Bradford University for one year as a research visitor where he obtained post doctorate degree. Dr. Ghorbani is author and coauthor of more than seventy papers in conferences as well as scientific journals.     

频率合成器的相位噪声分析

频率合成器被喻为雷达电子系统的"心脏",其相位噪声对设备和系统的性能影响很大.文中简单介绍了频率合成器相位噪声的基本概念.基于频率合成器的基本实现方法,分析了频率合成器中的相位噪声,通过实例说明了不同合成方式频率合成器的相位噪声.时频率合成器的低相噪声设计的工程实现有一定的指导意义.     

1.25 Gbit/s 0.25μm CMOS时钟恢复电路

1．25Gbit／s时钟恢复电路由TSMC0．25μm数字CMOS工艺实现。它包含鉴频鉴相器、环路滤波器及压控振荡器。压控振荡器采用一种改进型四级环形振荡器结构,具有正交输出,在其较宽调谐范围内输出电压摆幅恒定。该电路工作速率为1．03—1．4Gbit／s。在恢复时钟频率为1．25GHz时测量的时钟有效值抖动为4．6ps。     

一种新型低功耗CMOS压控振荡器采用电感偏置实现高性能的FoM

A novel voltage-controlled oscillator(VCO) topology with low voltage and low power is presented. It employed the inductive-biasing to build a feedback path between the tank and the MOS gate to enhance the voltage gain from output nodes of the tank to the gate node of the cross-coupled transistor. Theoretical analysis using timevarying phase noise theory derives closed-form symbolic formulas for the 1/f~2 phase noise region, showing that this feedback path could improve the phase noise performance. The proposed VCO is fabricated in TSMC 0.13 m CMOS technology. Working under a 0.3 V supply voltage with 1.2 m W power consumption, the measured phase noise of the VCO is –119.4 d Bc/Hz at 1 MHz offset frequency from the carrier of 4.92 GHz, resulting in an Fo M of 192.5 d Bc/Hz.     

小样本下自校正卷积神经网络的滚动轴承故障识别方法

针对实际工程中因故障样本数据稀少而导致模型识别准确率不高的问题,提出了一种基于自校正卷积神经网络(SC-CNN)的滚动轴承故障诊断模型,并将其应用于小样本条件下的故障识别研究。首先,为减少不同信号的数据分布差异,在每个卷积层后添加BN算法;其次,利用自校正卷积学习信号的多尺度特征,提高模型获取有用故障特征的能力;然后,引入通道自注意力机制,建立通道特征信息之间的相关性,用于突出故障特征并抑制数据过拟合;再将少量训练样本输入到模型中进行学习;最后,将各类不同条件下的故障信号输入到训练好的SC-CNN模型进行识别分类,并在两个数据集上进行实验验证。结果表明,所提模型在信噪比为-4 dB的强噪声环境下,识别准确率分别为98.64%和99.83%,在变工况条件下,识别准确率分别为94.37%和99.64%,验证了SC-CNN模型在小样本条件下具有较强的鲁棒性和泛化性能。     

基于对称螺旋型电感和差分二极管的2.4GHz CMOS正交输出压控振荡器

提出了一种产生2.4GHz正交本地振荡信号的方法.它将LC-VCO和两级环路振荡器两种结构组合起来以实现正交输出的低相位噪声压控振荡器.LC网络是由在片对称螺旋型电感和差分二极管组成的.详细论述了VCO原理及其噪声性能.该电路已经用0.25μm单层多晶、五层金属N阱CMOS数字工艺制作.测量结果表明:它可以提供正交的本地振荡信号,其振荡频率可以在300MHz的范围内调节,当仅对差分输出振荡信号的一端进行测试时,振荡频率为2.41GHz时,去偏移中心为600kHz时的相位噪声为-104.33dBc/Hz.而且,它能在很低的电源电压下工作,功耗也很低,所以,它在集成收发机中将得到广泛的应用.     

A 2.4GHz Quadrature Output Frequency Synthesizer

A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0.35μm CMOS technology are presented.A differentially controlled quadrature voltage-controlled oscillator (QVCO) is employed to generate quadrature (I/Q) signals.A second-order loop filter,with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost.The measured spot phase noise is –106.15dBc/Hz@1MHz.Close-in phase noise is less than -70dBc/Hz.The synthesizer consumes 13.5mA under a 3.3V voltage supply.The core size is 1.3mm×0.8mm.     

低抖动时钟锁相环的一种优化设计方法

重点分析了环路延迟对锁相环稳定性和输出信号抖动性能的影响,提出了一个简单的优化设计方法。用90nmCMOS工艺设计实现了一个基于自偏置技术的时钟锁相环,锁相环可以在很宽的输入频率范围内输出低抖动的时钟信号。     

低抖动的480 MHz CMOS电荷泵式锁相环

本文设计了一款用于USB2.0时钟发生作用的低抖动、低功耗电荷泵式锁相环电路。其电路结构包含鉴频/鉴相器、电荷泵、环路滤波器、压控振荡器和分频器。电路设计是基于CSM0.18μmCMOS工艺,经HSPICE仿真表明,锁相环输出480MHz时钟的峰峰值抖动仅为5.01ps,功耗仅为8.3mW。