低相位噪声压控振荡器设计

分析了LC压控振荡器(VCO)相位噪声,通过改进电路结构,采用PMOS和NMOS管做负阻管,在尾电流源处加入电感电容滤波,优化电感设计,设计了一种高性能压控振荡器.采用TSMC 0.18 μm IP6M CMOS RF工艺,利用Cadence中的Spectre RF工具对电路进行仿真.在电路的偏置电流为6 mA、电源电压VDD=1.8 V时,输入控制电压为0.8～1.8 V,输出频率变化为1.29～1.51 GHz,调谐范围为12.9%,相位噪声为-134.4 dBc/Hz@1MHz,功耗仅为10.8 mW.     

基于FPGA 的K 波段VCO 宽带线性校正

为解决K波段宽带线性校正器件复杂、成本高、调试难等问题,提出了一种基于FPGA的VCO开环线性校正方法.利用VCO电调特性的开环线性校正原理,采用FPGA控制D/A芯片对VCO的电调特性进行开环宽带线性校正,同时通过控制FPGA产生的时钟,产生任意时宽的线性调频连续波,并进行试验测试.测试结果表明:在带宽为400 MHz时的非线性度小于0.1%,开环线性校正实现方案简单、成本小,满足系统指标要求.     

Ka频段鳍线电调振荡器

介绍了一种由鳍线、耿氏器件和梁式引线变容管构成的混合集成电调振荡器电路及其设计方法．给出的ＶＣＯ电路结构简单,利用其等效电路模型,可方便地对振荡器在所需工作频率上的电调带宽进行优化设计．经优化设计的电调振荡器性能的测试结果为：在３４．９３ＧＨｚ的频率处,具有１．２ＧＨｚ的电调带宽,带内功率输出为２０．６５±０．５２ｄＢｍ．     

A high-speed bit synchronization circuit by direct control of the oscillation phase of a VCO

In a large-scale broadband communication system, thousands of high-speed serial data interconnections are used and a bit synchronization circuit (a clock and data recovery circuit) is required in each of the receiver side interconnection circuits. In this paper, the requirements and the implementation of a bit synchronization circuit for the interconnection are considered, and one solution is proposed. In the proposed circuit, the oscillation phase of a VCO is directly controlled by the trigger signal extracted from the input data. Synchronization capture is quick and the circuit is applicable to burst signals. The circuit tolerates jitter and phase variation of the incoming data. The circuit requires no external components, and is suitable for an integrated circuit. The circuit was implemented using a 0.5 μm CMOS process and the data recovery operation from a 440 Mbps pseudo-random pattern was confirmed. Data acquisition is accomplished within three clock periods from 440 Mbps burst data. © 1998 Scripta Technica, Electr Eng Jpn, 125(2): 35–43, 1998     

2.45 GHz 0.8 mW voltage-controlled ring oscillator (VCRO) in 28 nm fully depleted silicon-on-insulator (FDSOI) technology

MOS bulk transistor is reaching its limits: sub-threshold slope (SS), drain induced barrier lowering (DIBL), threshold voltage (VT) and VDD scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Fully depleted devices are mandatory to continue the technology roadmap. FDSOI technology relies on a thin layer of silicon that is over a buried oxide (BOx). Called ultra thin body and buried oxide (UTBB) transistor, FDSOI transistors correspond to a simple evolution from conventional MOS bulk transistor. The capability to bias the back-gate allows us to implement calibration techniques without adding transistors in critical blocks. We have illustrated this technique on a very low power voltage-controlled oscillator (VCO) based on a ring oscillator (RO) designed in 28 nm FDSOI technology. Despite the fact that such VCO topology exhibits a larger phase noise, this design will address aggressively the size and power consumption reduction. Indeed we are using the efficient back-gate biasing offered by the FDSOI MOS transistor to compensate the mismatches between the different inverters of the ring oscillator to decrease jitter and phase noise. We will present the reasons which led us to use the FDSOI technology to reach the specifications of this PLL. The VCRO exhibits a 0.8 mW power consumption, with a phase noise about --94 dBc/Hz@1 MHz.     

紧凑型Ka波段PHEMT微波单片集成VCO

设计并流片制作了基于GaAs PHEMT工艺的Ka波段微波单片集成压控振荡器(MMIC VCO).该VCO具有紧凑、宽电调谐带宽及高输出功率的特点.提出了缩小芯片面积及增大调谐带宽的方法,同时还给出了设计MMIC VCO的基本步骤.该方法设计并流片制做的MMIC VCO的测量结果为:振荡频率为36±1.2GHz,输出功率为10士1dBm,芯片面积为1.3mm×1.0mm.     

Low Phase Noise VCO using Novel Harmonic Control Circuit Based on Quad-band Composite Right/Left-handed Transmission Line

In this paper,a novel Voltage-Controlled Oscillator(VCO)using the harmonic control circuit based on the quad-band Composite Right/Left-Handed(CRLH)Transmission Line(TL)is presented to reduce the phase noise without the reduction of the frequency tuning range and miniaturizing the circuit size.The phase noise has been reduced by the quad-band harmonic control circuit which has the short impedance for the second-and third-and fourth-and fifth-harmonic components.The CRLH TL with two Left-Handed(LH)(backward)and two Right-Handed(RH)(forward)pass bands are used to design the quad-band harmonic control circuit.The high-Q resonator has been used to reduce the phase noise,but it has the problem of the frequency tuning range reduction.However,the frequency tuning range of the proposed VCO has not reduced because the phase noise has reduced without the high-Q resonator.The miniaturization of the circuit size is achieved by using the quad-band CRLH TL instead of the conventional RH TL.The phase noise of VCO is-124.43～-122.67 dBc/Hz at 100 kHz in the tuning range of 5.729～5.934 GHz.     

一种新型的双端加载宽带压控振荡器

基于某测试系统宽带本振的指标要求,设计了一种双端加载可变电容的宽带压控振荡器(VCO),采取负阻分析法对电路结构进行分析设计,采用ADS对电路进行仿真设计,并通过实物验证设计结果的真实性和有效性。设计指标:频率为2.00～3.30GHz,相位噪声指标小于-80dBc/Hz@10kHz,输出功率大于5dBm。     

基于开关电容阵列的5.8GHz全集成LC压控振荡器设计

采用TSMC 0.18μm 1P6M RF CMOS工艺,完成了一种基于开关电容阵列的全集成LC压控振荡器的设计.版图后仿真结果表明,在1.8V电源电压下,电路核心功耗约为7.2mW,中心振荡频率为5.8GHz,在偏离中心频率1MHz处,该VCO的相位噪声为-121.8dBc/Hz,调谐范围为10.2%,满足交通专用短程通信系统的频段要求.     

ADF4111在锁相式频率源中的应用

为了得到射频接收机中稳定的频率源,设计了一种以ADF4111为核心的锁相式频率源,采用单片机进行控制。介绍了锁相环芯片ADF4111的基本结构、工作原理及其编程控制过程,同时介绍了环路滤波器和压控振荡器的设计。测试表明该频率源的工作频率为754 MHz～764MHz,频率步进为100kHz,相位噪声优于-90dBc/Hz@10kHz、-110 dBc/Hz@100kHz,输出功率为6dBm。