2,7‐Carbazolenevinylene‐Based Oligomer Thin‐Film Transistors: High Mobility Through Structural Ordering

We have fabricated organic field‐effect transistors based on thin films of 2,7‐carbazole oligomeric semiconductors 1,4‐bis(vinylene‐(N‐hexyl‐2‐carbazole))phenylene (CPC), 1,4‐bis(vinylene‐(N′‐methyl‐7′‐hexyl‐2′‐carbazole))benzene (RCPCR), N‐hexyl‐2,7‐bis(vinylene‐(N‐hexyl‐2‐carbazole))carbazole (CCC), and N‐methyl‐2,7‐bis(vinylene‐(7‐hexyl‐N‐methyl‐2‐carbazole))carbazole (RCCCR). The organic semiconductors are deposited by thermal evaporation on bare and chemically modified silicon dioxide surfaces (SiO₂/Si) held at different temperatures varying from 25 to 200 °C during deposition. The resulting thin films have been characterized using UV‐vis and Fourier‐transform infrared spectroscopies, scanning electron microscopy, and X‐ray diffraction, and the observed top‐contact transistor performances have been correlated with thin‐film properties. We found that these new π‐conjugated oligomers can form highly ordered structures and reach high hole mobilities. Devices using CPC as the active semiconductor have exhibited mobilities as high as 0.3 cm² V^–1 s^–1 with on/off current ratios of up to 10⁷. These features make CPC and 2,7‐carbazolenevinylene‐based oligomers attractive candidates for device applications.     

The Cooperative Molecular Field Effect

Two‐dimensional arrangements of molecules can show remarkable cooperative electronic effects. Such effects can serve to achieve direct electronic sensing of chemical and physical processes via electrostatic effects, i.e., without transfer of charge or matter between the locus of sensing and that of detection.     

Inside Front Cover: Freely Suspended Layer‐by‐Layer Nanomembranes: Testing Micromechanical Properties (Adv. Funct. Mater. 5/2005)

A study of the micromechanical properties of layer‐by‐layer nanomembranes composed of a center layer of gold nanoparticles is reported by Tsukruk and co‐workers on p. 771. The micro‐ and nanomechanical properties of these membranes are measured using a combination of resonance‐frequency tests, bulging tests, and point‐load nanodeflection experiments. These freely suspended nanomembranes (right) with an elastic modulus of 5–10 GPa are very robust and can sustain multiple significant deformations (left, image obtained by B. Rybak and P. Kladitis). They are sensitive to variations in pressure and therefore have potential applications in pressure and acoustic sensors. Freely suspended nanocomposite layer‐by‐layer (LbL) nanomembranes composed of a central layer of gold nanoparticles sandwiched between polyelectrolyte multilayers are fabricated via spin‐assisted LbL assembly. The diameter of the circular membranes is varied from 150 to 600 μm and the thickness is kept within the range of 25–70 nm. The micro‐ and nanomechanical properties of these membranes are studied using a combination of resonance‐frequency and bulging tests, and point‐load nanodeflection experiments. Our results suggest that these freely suspended nanomembranes, with a Young's modulus of 5–10 GPa are very robust and can sustain multiple significant deformations. They are very sensitive to minor variations in pressure, surpassing ordinary semiconductor and metal membranes by three to four orders of magnitude and therefore have potential applications as pressure and acoustic microsensors.     

Analysis and simulation of interrupt overhead impact on OS throughput in high‐speed networks

The paper presents analytical and simulation models to study the impact of interrupt overhead on operating system throughput of network elements such as PC‐based routers, servers, and hosts when subjected to high‐speed network traffic. Under such high network traffic, the system throughput will be negatively affected due to interrupt overhead caused by the incoming traffic. We first present an analytical model for the ideal system when interrupt overhead is ignored. We then present two models which describe the impact of high interrupt rate on system throughput. One model is for employing PIO in which network adapters are not equipped with DMA engines, and the other model is for employing DMA in which network adapters are equipped with DMA engines. The paper also describes detailed discrete‐event simulation models for the ideal system and for systems with DMA and PIO. Simulations results as well as reported experimental measurements show that our analytical models are valid and give a good approximation. Our analysis and simulation work can be valuable in providing insight to understand and predict system behaviour, as well as improving and maintaining good host performance. The paper identifies analytically critical design operation points such as that of overload condition. The paper also proposes solutions and recommendations for improving performance. Copyright © 2005 John Wiley & Sons, Ltd.     

The Region 1 & 3 Broadcasting‐Satellite Service Plan after WRC‐03

The 1977 Broadcasting‐Satellite Service (BSS) Plan for Region 1 & 3 had been widely acknowledged to be out‐of‐date by the late 1980s. Development of digital modulation in the early 1990s provided an opportunity to update the technical provisions of the Plan to make it more economically viable. After a decade of work and three World Radiocommunication Conferences (WRCs), the revision of Region 1 & 3 BSS Plan was finally completed in 2003. The new Plan increased channel assignments from 5 to 10 analog‐equivalent channels for each country in Region 1, and from 4 to 12 channels for each country in Region 3. Yet, despite the increase in capacity, the new Plan is surprisingly similar to the original one in terms of the technical parameters. It is still based on national coverage, and the channel plan, orbital location, orbital spacing, and polarization are also the same. As a result, the new Plan is no more economically viable to implement than the old. To create economically viable BSS systems would most likely require modifications to the assignment in the Plan. Yet, modification procedures were made more difficult to apply after replanning. Less future implementation of BSS networks than would otherwise have occurred can be expected, and an inefficient usage of these frequency bands will likely result. On the other hand, less implemented systems will mean more capacity set aside for future use. This is important for countries that currently do not have satellite operations. In the end, BSS replanning reflects the eternal conflict between efficient usage and guaranteed future access. Copyright © 2005 John Wiley & Sons, Ltd.     

Performance evaluation on a double‐layered satellite network

How to evaluate the performance of satellite networks is a prerequisite to the construction of satellite networks, and is also one of challenges in the researches on satellite networks. In this paper, generalized stochastic Petri net (GSPN) models are presented to carry out the performance analysis of a double‐layered satellite network. Firstly, the GSPN model of a double‐layered satellite network is simplified by proper analysis. Then, two sets of experiments are conducted to analyse the performance of the satellite networks, and show that the double‐layered satellite network outperforms single‐layered ones on the heavy traffic load. Finally, the feasibility and effectiveness of the proposed approach is verified by simulation experiments. Copyright © 2005 John Wiley & Sons, Ltd.     

Voltage‐Mode 1.5 Gbps Interface Circuits for Chip‐to‐Chip Communication

In this paper, interface circuits that are suitable for point‐to‐point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi‐gigabits per‐second between two chips with a point‐to‐point interconnection, the input receiver uses an on‐chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode‐connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 µm dual gate oxide CMOS technology.     

利用Gibbs采样的同频混合信号单通道盲分离

针对非合作接收的单通道同频数字调制混合信号,提出一种基于Gibbs采样的分离算法。该算法利用统计的方法获得未知符号序列概率密度的随机样本,运算复杂度随信道阶数的增加不呈指数增长。重点研究了基于单符号对、多符号对的分离算法和信道响应的跟踪,并对Gibbs分离算法和PSP分离算法的性能进行了详细的分析比较。仿真结果表明,针对2路QPSK调制的混合信号,在与L=4时的PSP算法具有近似分离性能的同时,Gibbs分离算法可使复杂度降低近17倍。     

用于光子计数的InGaAs/InP SPAD设计

重点研究了InGaAs/InP SPAD的隧道贯穿电场、雪崩击穿电场、雪崩宽度与过偏电压的关系,提出了过偏电压的计算方法.分析了InGaAs/InP SPAD的基本特性即探测效率、暗计数率与其过偏电压、工作温度、量子效率、电场分布的依赖关系,提出了一种单光子InGaAs雪崩二极管的设计方法.设计制作了InGaAs/InP SPAD,并在门控淬灭模式下进行了单光子探测实验.结果表明:对于200m的SPAD,在过偏2 V、温度-40 ℃条件下,探测效率(PDE) 20%(1 550 nm)、暗计数率(DCR)20 kHz;对于50m的SPAD,在过偏2.5 V、温度-40 ℃条件下,探测效率(PDE) 23%(1 550 nm)、暗计数率(DCR)2 kHz.最后对实验结果进行了分析和讨论.     

基于不完备CSI的OFDMA公平资源分配算法

针对在信道状态信息不完备时,很难兼顾系统容量和公平性这一问题,通过引入公平松弛因子,提出一种公平性可调的遍历容量最大化资源分配算法。为了降低计算复杂度,在利用对偶优化方法求解拉格朗日算子过程中,提出同层循环迭代的搜索方式以代替传统的内外层循环迭代方式。通过仿真和分析表明,该算法在满足公平性的同时实现了遍历容量最大化,且计算复杂度明显降低。