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61.
低渗透油藏生产井关井测压时间的计算与应用 总被引:4,自引:4,他引:0
低渗透油藏的生产井压裂后,在单井试油试采过程中,压力恢复测试关井时间不同,其中有些井压力恢复曲线不能出现边界反应段,渗流不能反映地层中真实流动特征。针对这种情况,基于长庆绥靖油田塞39井区长:低渗透油藏大量试井和实际生产资料,利用现代试井解释理论,研究合理关井时间的界限及其计算方法。结果表明,当油井关井测压时间达到3倍地层径向流开始出现的时间后,利用此时的压力数据解释地层参数和地层压力,其结果的误差小于5%,同时能较准确地判断边界类型。计算的理论曲线和霍纳法解释值非常接近,对于塞39井区,若预先知道某生产井地层有效渗透率值,可从理论曲线查出压力恢复试井的关井时间,否则,建议按照该井区地层有效渗透率(大约在6mD左右),将不稳定试井测试时间控制在25d以上为宜。图4表3参14 相似文献
62.
When a circuit is tested using random or pseudorandom patterns, it is essential to determine the amount of time (test length) required to test it adequately. We present a methodology for predicting different statistics of random pattern test length. While earlier methods allowed estimation only of upper bounds of test length and only for exhaustive fault coverage, the technique presented here is capable of providing estimates of all statistics of interest (including expected value and variance) for all coverage specifications.Our methodology is based on sampling models developed for fault coverage estimation [1]. Test length is viewed as awaiting time on fault coverage. Based on this relation we derive the distribution of test length as a function of fault coverage. Methods of approximating expected value and variance of test length are presented. Accuracy of these approximations can be controlled by the user. A practical technique for predicting expected test length is developed. This technique is based on clustering faults into equal detectability subsets. A simple and effective algorithm for fault clustering is also presented. The sampling model is applied to each cluster independently and the results are then aggregated to yield test lengths for the whole circuit. Results of experiments with several circuits (both ISCAS '85 benchmarks and other practical circuits) are also provided.This work was done while the author was with the Department of Electrical Engineering, Southern Illinois University, Carbondale, IL 62901. 相似文献
63.
Energy minimization and design for testability 总被引:6,自引:0,他引:6
Srimat T. Chakradhar Vishwani D. Agrawal Michael L. Bushnell 《Journal of Electronic Testing》1994,5(1):57-66
The problem of fault detection in general combinational circuits is NP-complete. The only previous result on identifying easily testable circuits is due to Fujiwara who gave a polynomial time algorithm for detecting any single stuck fault inK-bounded circuits. Such circuits may only contain logic blocks with no more thanK input lines and the blocks are so connected that there is no reconvergent fanout among them. We introduce a new class of combinational circuits called the (k, K)-circuits and present a polynomial time algorithm to detect any single or multiple stuck fault in such circuits. We represent the circuit as an undirected graphG with a vertex for each gate and an edge between a pair of vertices whenever the corresponding gates have a connection. For a (k, K)-circuit,G is a subgraph of ak-tree, which, by definition, cannot have a clique of size greater thank+1. Basically, this is a restriction on gate interconnections rather than on the function of gates comprising the circuit. The (k, K)-circuits are a generalization of Fujiwara'sK-bounded circuits. Using the bidirectional neural network model of the circuit and the energy function minimization formulation of the fault detection problem, we present a test generation algorithm for single and multiple faults in (k, K)-circuits. This polynomial time aggorithm minimizes the energy function by recursively eliminating the variables. 相似文献
64.
本文从三级像差理论出发,推导了几种工艺球面检验凸二次曲面的计算公式。根据这些公式计算结果,进行了光路追迹,给出了这些公式对凸二次曲面的补偿范围;并讨论了几种特殊情况下的平面解。 相似文献
65.
在分析转向柱管花键部位应力集中情况的基础上,通过对某厂生产的转向柱管扭转破坏的试验研究,得到如下结论:①转向柱管的承载能力与其外花键齿与方向盘中心内花键齿之间的非接触区长度有关,以花键端部过渡圆弧的直径大小为宜;②安装方向盘总成时所施加在安装螺母上的拧紧力矩在70N.m左右时,转向柱管的承载能力最大。 相似文献
66.
An analysis is presented on development, production, and use of high-capacity weighing machines in Russia in the last ten years. Aspects arising in type approval testing are considered for high-capacity weighing machines working over wide temperature ranges. 相似文献
67.
Ozgur Sinanoglu Ismet Bayraktaroglu Alex Orailoglu 《Journal of Electronic Testing》2003,19(4):457-467
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme. 相似文献
68.
洁净型煤技术开发研制 总被引:4,自引:0,他引:4
通过对洁净型煤技术的介绍,并对型煤质量及燃烧测试分析,认为洁净型煤技术是一种煤的高效洁净燃烧、改善环境空气质量及节约能源的有效技术。 相似文献
69.
70.