基于测试性设计特性的样本量确定方法

针对测试性验证试验方法的局限性,提出了一种新的故障样本量的确定方法。根据系统的测试性特性,建立单元、功能、性能和测试之间的相关矩阵;选择相关矩阵的列权值最大的列删减单元功能相关矩阵和功能性能相关矩阵,依次遍历完所有列,获取样本和样本数量;利用实例进行了验证,结果表明：计算过程简单,结果更符合实际系统测试性验证试验对于样本量的要求。     

基于MCU的可测试性设计

根据ＭＣＵ结构非常复杂且具有指令系统的特点,没有采用一般数字电路设计的从结构出发的ＤＦＴ技术,而是设定了ＭＣＵ的３种工作模式,提出了一种在ＭＣＵ中加入规模很小的模式选择电路,对部分电路作较小改动,就可以对芯片内的各块电路进行功能测试的方法。在完成了ＭＣＵ的可测性设计后进行了仿真,结果表明电路能正常工作在各种模式下。     

测试性验证中正态分布法改进

文中改进了测试性验证中的正态分布法,通过添加试验前计算,完全消除试验后计算,直接给出抽样方案。     

Test Vector Optimization Using Pocofan-Poframe Partitioning

This paper presents an automated POCOFAN-POFRAME algorithm that partitions large combinational digital VLSI circuits for pseudo exhaustive testing. In this paper, a simulation framework and partitioning technique are presented to guide VLSI circuits to work under with fewer test vectors in order to reduce testing time and to develop VLSI circuit designs. This framework utilizes two methods of partitioning Primary Output Cone Fanout Partitioning (POCOFAN) and POFRAME partitioning to determine number of test vectors in the circuit. The key role of partitioning is to identify reconvergent fanout branch pairs and the optimal value of primary input node N and fanout F partitioning using I-PIFAN algorithm. The number of reconvergent fanout and its locations are critical for testing of VLSI circuits and design for testability. Hence, their selection is crucial in order to optimize system performance and reliability. In the present work, the design constraints of the partitioned circuit considered for optimization includes critical path delay and test time. POCOFAN-POFRAME algorithm uses the parameters with optimal values of circuits maximum primary input cone size (N) and minimum fan-out value (F) to determine the number of test vectors, number of partitions and its locations. The ISCAS’85 benchmark circuits have been successfully partitioned, the test results of C499 shows 45% reduction in the test vectors and the experimental results are compared with other partitioning methods, our algorithm makes fewer test vectors.     

基于TMS320C54x的机内测试测试性验证系统

通过故障注入的方式检测测试系统的性能是一种有效的验证系统测试性水平的方法．本文提出了一种基于TMS320C54x的机内测试（Built-in Test,BIT）测试性验证系统的设计方案,给出了系统实现的基本原理以及总体结构框图、工作流程图、原理图等设计．故障注入系统是BIT测试性验证系统的核心部分,经试验证明采用基于TMS320C54x将测试性验证系统以平台化方式实现的设计,能够满足验证BIT测试性的要求,并有效地降低了设计复杂度,达到了预期的设计目的．     

雷达系统软件可测试性研究

作为提高雷达软件系统可靠性的重要手段,软件可测试性一直都是该领域研究人员关注的热点和难点。文章阐述软件可测试性在现有雷达系统中的重要性、现状以及存在的不足,分析在现代雷达系统设计过程中提升软件可测试性的方法,为提高雷达系统中软件测试效率和质量提供支持。     

基于贝叶斯网络的系统测试性建模与分析

针对现有测试性建模方法对系统不确定信息描述及分析上的不足,提出了基于贝叶斯网络的测试性建模与分析方法。首先结合贝叶斯网络的基本理论,阐述了系统测试性模型的构成要素及建立流程,用相关性矩阵表示系统故障-测试之间的关联,用条件概率矩阵描述两者间的不确定信息;然后给出了测试性指标的具体分析过程和算法;最后通过实例验证了方法的有效性。     

商务群替代小交换机的方案及实现

本文介绍了用中兴ZXJ10交换机的商务群功能替代厂内部模拟小交换机的实现方案,描述了实现方案的具体施工过程和交换机数据系统的设置方法和步骤,以达到改善整个厂内部通话的目的。     

改进信息熵算法的最优测试序列生成方法

测试性设计和分析中的一个重要问题是构建一种测试序列,获得满足需求的故障隔离精度并降低测试代价.目前已提出多种研究算法,如信息熵算法、AO＊算法等,但都存在一些问题.针对测试序列问题,对不同方法进行研究,针对已有算法的不足,在信息熵理论的基础上,提出了一种一步前向回溯算法,即改进信息熵算法,并给出具体的计算步骤.该算法既可应用于二值属性系统,又适用于多值属性系统.实例计算结果和算法分析表明,此算法和已有算法相比,该算法简单,计算时间短,测试代价最优,具有很好的实用价值.     

Demonstration of an Analog IC Function Maintenance Strategy, Including Direct Calibration, Built-in Self-test, and Commutation of Redundant Functional Blocks

A new analog subsystem maintenance strategy is presented that can be used to improve the accuracy, reliability, yield, and testability of analog and mixed-signal ICs. This scheme is a generally applicable design approach that combines hybrid redundancy, direct subcircuit parameter adjustment (calibration), and on-chip analog function verification (built-in self-test). Improvements are realized in a system-transparent fashion through careful function block commutation. The cost is a moderate die area increase. This design strategy is applicable to a wide range of moderately complex analog functions. An example analog function is used here to illustrate this new maintenance approach. Experimental data demonstrate the capabilities of this new approach to analog IC design fortestability.