叠层压敏电阻器的近期研制动向

从构成叠层压敏电阻器的生片材料（材料晶粒大小、生片厚度）、内电极材料、叠层结构和表面处理等方面，介绍叠层压敏电阻器的近期研制动向。     

SrTiO3环型压敏电阻器的研制及商品化生产

采用液氨分解制备的75％H2 25％N2混合气体形成还原性气氛，同时掺杂Nb2O5等添加剂使晶粒半导化，通过在空气中热处理使晶界绝缘，制得SrTiO3环型压敏电阻器，并在国内较早投入大规模商品化生产．笔者对产品进行了常规电性能测试，特殊试验及寿命试验，井与国内外同类产品进行了比较。结果表明：产品主要电气性能达到或接近国外同类产品水平，成品率达到90％以上。     

三氧化钨基低压电容–压敏电阻及其稳定性研究

介绍了一种新型的WO3基(电容–压敏双功能)压敏电阻的优点,及阻碍其广泛应用的原因。指出电学性能的不稳定性来源于相结构的两相共存,稀土掺杂可使其相结构单一化,从而稳定其电学性能。有望使我国的钨资源优势转化为产品优势。     

ZnO压敏电阻器用电气绝缘粉末固化物吸水特性的研究

ZnO压敏电阻器的耐湿热劣化性能主要决定于电气绝缘粉末固化物的吸水特性和透水特性,研究了电气绝缘粉末固化物在恒温恒湿条件下的吸水规律,指出其初期符合费克第二定律,经过一定受潮时间后趋于饱和。实验表明,吸水后介电常数和介质损耗角正切增大,国外和部分国产试样吸水后高频区和低频区的介电常数和介质损耗角正切基本同步增加,但是另一部分国产试样低频区的介质损耗角正切增长幅度大于高频区,这可能是水分子引起的可动离子造成的离子电导所致。     

Recent Progress in Applications of the Cold Sintering Process for Ceramic–Polymer Composites

Ceramic–polymer composites are of interest for designing enhanced and unique properties. However, the processing temperature windows of sintering ceramics are much higher than that of compaction, extrusion, or sintering of polymers, and thus traditionally there has been an inability to cosinter ceramic–polymer composites in a single step with high amounts of ceramics. The cold sintering process is a low‐temperature sintering technology recently developed for ceramics and ceramic‐based composites. A wide variety of ceramic materials have now been demonstrated to be densified under the cold sintering process and therefore can be all cosintered with polymers from room temperature to 300 °C. Here, the status, understanding, and application of cold cosintering, with different examples of ceramics and polymers, are discussed. One has to note that these types of cold sintering processes are yet new, and a full understanding will only emerge after more ceramic–polymer examples emerge and different research groups build upon these early observations. The general processing, property designs, and an outlook on cold sintering composites are outlined. Ultimately, the cold sintering process could open up a new multimaterial design space and impact the field of ceramic–polymer composites.     

Non‐Ohmic Properties and Electrical Responses of Grains and Grain Boundaries of Na1/2Y1/2Cu3Ti4O12 Ceramics

The dielectric and non‐Ohmic properties of Na_1/2Y_1/2Cu₃Ti₄O₁₂ ceramics sintered under various conditions to obtain different microstructures were investigated. Microstructure analysis confirmed the presence of Na, Y, Cu, Ti, and O and these elements were well dispersed in the microstructure. Na_1/2Y_1/2Cu₃Ti₄O₁₂ ceramics exhibited non‐Ohmic characteristics with large nonlinear coefficients of about 5.7–6.6 irrespectively of sintering conditions. The breakdown electric field of fine‐grained ceramic with the mean grain size of ≈1.7 μm (≈5600 V/cm) was much larger than those of the course‐grained ceramics with grain sizes of ≈9.5–10.4 μm (≈1850–2180 V/cm). Through optimization of sintering conditions, a low loss tangent of about 0.03 and very high dielectric permittivities of 18 000–23 000 with good temperature stability were successfully accomplished. The electrical responses of the grains and grain boundaries can, respectively, be well described using admittance and impedance spectroscopy analyses based on the brickwork layer model. A possible mechanism for the origin of semiconducting grains is discussed. The colossal dielectric response was reasonably described as closely correlated with the electrically heterogeneous microstructure by means of strong interfacial polarization at the insulating grain‐boundary layers. The non‐Ohmic properties of Na_1/2Y_1/2Cu₃Ti₄O₁₂ ceramics were primarily related to their microstructure, i.e., grain size and volume fraction of grain boundaries.     

Ce掺杂的TiO_2电容-压敏材料结构和电性能研究

通过对样品压敏性能、介电性能的测定和晶体结构、表面形貌分析,研究了CeO2对TiO2电容-压敏电阻器的影响。研究发现CeO2对TiO2电容-压敏电阻的性能有显著的影响。在1350℃烧结条件下,0.4%摩尔分数CeO2的样品表现出优良的综合电性能,其压敏电压为15.84V/mm,非线性系数α为4.62,并具有很高的表观介电常数(εr=158600),较低的介电损耗(tgδ=0.32),是一种较有潜力的新型电容-压敏电阻器。     

烧结条件对TiO_2压敏陶瓷性能的影响

本文研究了烧结温度和保温时间对TiO2压敏陶瓷微观结构和电学性能的影响;用扫描电子显微镜(SEM)观察了样品的微现形貌;用X射线衍射(XRD)表征了样品的物相、晶体结构.结果表明:用一次直接烧结法制备的TiO2压敏陶瓷,以1350℃烧结2h样品的性能最佳,具有最优微结构和性能.烧结温度与保温时间两者之间在一定程度上相互制约,因此必须严格控制最高烧成温度和保温时间,在一定烧结条件下获得致密的微观结构以及较好的电学特性.     

低压ZnO压敏陶瓷晶粒边界电子陷阱态的研究

应用４１９２Ａ低频阻抗分析仪测量了低压ＺｎＯ压敏陶瓷的复电容曲线,研究了烧结温度对复电容曲线压低角的影响规律,探讨了晶粒边界耗尽层中电子陷阱的种类和起因并对电子陷阱的特征参数进行了表征．实验发现：在低压ＺｎＯ压敏陶瓷中存在两种非理想的Ｄｅｂｙｅ弛豫现象,对于每一种弛豫,其复电容曲线存在压低现象,且其压低角随着烧结温度的升高而迅速减小．在低压ＺｎＯ压敏陶瓷的耗尽层区域内存在两种电子陷阱,它们分别位于导带底０．２０９和０．３４２ｅＶ处,其中０．２０９ｅＶ处的陷阱能级对应于本征施主Ｚｎ×ｉ的二次电离,而０．３４２ｅＶ处的陷阱能级对应于氧空位ＶＯ的一次电离．