Modular implementation of efficient self-checking checkers for the Berger code

A technique for designing efficient checkers for conventional Berger code is proposed in this paper. The check bits are derived by partitioning the information bits into two blocks, and then using an addition array to sum the number of 1's in each block. The check bit generator circuit uses a specially designed 4-input 1's counter. Two other types of 1's counters having 2 and 3 inputs are also used to realize checkers for variable length information bits. Several variations of 2-bit adder circuits are used to add the number of 1's. The check bit generator circuit uses gates with fan-in of less than or equal to 4 to simplify implementation in CMOS. The technique achieves significant improvement in gate count as well as speed over existing approaches.     

Thermal Monitoring of Self-Checking Systems

With the increasing power density in integrated systems resulting from scaling down, the occurrence of field failures due to overheating has considerably increased. Faulty operation can be prevented by on-line temperature monitoring. This paper deals with questions of on-line temperature monitoring in safety-critical systems. First the possible temperature sensors are reviewed and basic principles of self-checking systems including such sensors are detailed, then a new temperature sensor cell with extremely good parameters designed especially for DfTT applications is presented. The basic questions of integrating thermal sensors into self-checking systems are also discussed.     

Shorts in self-checking circuits

It has been noted by several authors that the classical stuck-at logical fault model might not be an appropriate representation of certain real failures occurring in integrated circuits. Shorts are an important class of such faults. This article gives a detailed analysis of the effects of shorts in self-checking circuits and proposes techniques for dealing with them. More precisely, we show that, unlike other faults such as stuck-at, stuck-on, and stuck-open—which produce only single errors in the place they occur—shorts can produce double errors on the two shorted lines. In particular, feedback shorts can produce double errors on the two shorted lines. The double error is unidirectional for some feedback shorts and non-unidirectional for some others. Furthermore, in some technologies (e.g., CMOS), non-feedback shorts can also produce double non-unidirectional errors. We also show that unlike stuck-at, stuck-on, and stuck-open faults, redundant shorts can destroy the SFS property. Then we propose several techniques for coping with these problems and we illustrate the results by circuit implementation examples.The present study is given for NMOS and CMOS circuits but we show that it is valid for any other technology.     

Automated synthesis of multiple analog circuits using evolutionary computation for redundancy-based fault-tolerance

Analog circuits are one of the most important parts of modern electronic systems and the failure of electronic hardware presents a critical threat to the completion of modern aircraft, spacecraft, and robot missions. Compared to digital circuits, designing fault-tolerant analog circuits is a difficult and knowledge-intensive task. A simple but powerful method for robustness is a redundancy approach to use multiple circuits instead of single one. For example, if component failures occur, other redundant components can replace the functions of broken parts and the system can still work. However, there are several research issues to make the redundant system automatically. In this paper, we used evolutionary computation to generate multiple analog circuits automatically and then we combined the solutions to generate robust outputs. Evolutionary computation is a natural way to produce multiple redundant solutions because it is a population-based search. Experimental results on the evolution of the low-pass, high-pass and band-stop filters show that the combination of multiple evolved analog circuits produces results that are more robust than those of the best single circuit.     

Majority gates vs. general weighted threshold gates

In this paper we study small depth circuits that contain threshold gates (with or without weights) and parity gates. All circuits we consider are of polynomial size. We prove several results which complete the work on characterizing possible inclusions between many classes defined by small depth circuits. These results are the following:

基于特征互补图像的人脸识别仿真研究

研究人脸识别精度问题。由于人脸图像中存在大量干扰信息的缺点,而造成了人脸识别正确率下降,为了解决上述问题,提出了一种基于特征互补图像快速特征融合算法。算法通过对人脸图像的位平面切片图像分析,采用位平面图像分解法,通过各种合成策略构造多幅样本图像。并突出高位平面图像,采用两种加权策略将每一幅人脸图像样本都生成"特征互补图像"。然后,直接用图像的二维典型相关分析(2DCCA)法对两种特征互补图像进行特征抽取。最后通过在ORL国际标准人脸库上进行的实验,结果表明,高位平面图像的典型相关鉴别特征提高了正确识别率,并且因为摒弃了原始人脸图像的大部分干扰信息所以具有更强的鲁棒性。     

基于演化算法的奇偶校验器自动设计*

基于演化算法技术,提出一种新的设计思想,实现奇偶校验器的电路自动设计.实验证明,多目标演化算法具有较少的运算量和较高的效率,能自动设计出使用逻辑门数更少、延时更小的奇偶校验器.     

小型无人机机载两轴云台设计与实现

针对小型无人机功率和载荷有限这一特点,本文设计了一套小型无人机机载两轴云台,采用集成了三轴陀螺仪、三轴加速度计MPU6050作为云台姿态反馈元件,使用互补滤波进行姿态解算。由于传统小型无人机的云台采用伺服舵机作为驱动电机,舵机内部减速齿轮的回滞误差会导致拍摄画面晃动,因此采用无刷电机直接驱动云台。为了测试该系统的有效性,通过小型四旋翼挂载该两轴云台拍摄实验,实验结果表明该云台使拍摄画质更加平稳,验证了该系统的有效性。     

纳米电路交叉冗余容错技术研究

提出了一种针对纳米电路的数字电路容错设计新方法．该方法基于交叉冗余原理,利用两种二进制错误的不对称性,采用模块化方法对纳米电路进行容错设计．以阵列乘法器为例,采用新方法对电路进行设计和仿真,并结合实验结果与传统的可重构和三模冗余容错方法进行比较．交叉冗余方法无需检测模块及表决器,不会增加系统延时,并且在资源消耗方面远低于传统方法,对纳米电路尤其适用．     

L波段低噪声放大器的分析与设计

利用Advanced Design System（ADS）完成了L波段低噪声放大器（LNA）的设计。分析了实际电路可能产生的非连续性、寄生参数效应等因素对电路各个性能指标的影响,并针对这些因素利用ADS进行了电磁仿真计算,最后给出了放大器的仿真结果和最终电路及测试结果。采用ATF-35143器件设计,达到了预定的技术指标,工作频率1.21GHz,增益G大于14dB,噪声系数NF小于0.5 dB,输入1dB压缩点大于5dbm。