Experimental study on temperature stress calculation and temperature control optimization of concrete based on early age parameters

Temperature control curve is the key to achieving temperature control and crack prevention of high concrete dam during construction,and its rationality depends on the accurate measurement of temperature stress.With the simulation testing machine for the temperature stress,in the present study,we carried out the deformation process tests of concrete under three temperature curves：convex,straight and concave.Besides,we not only measured the early-age elastic modulus,creep parameters and stress process,but also proposed the preferred type.The results show that at early age,higher temperature always leads to greater elastic modulus and smaller creep.However,the traditional indoor experiments have underestimated the elastic modulus and creep development at early age,which makes the calculated value of temperature stress too small,thus increasing the cracking risk.In this study,the stress values of the three curves calculated based on the strain and early-age parameters are in good agreement with the temperature stress measured by the temperature stress testing machine,which verifies the method accuracy.When the temperature changes along the concave curve,the law of stress development is in consistent with that of strength.Under this condition,the stress fluctuation is small and the crack prevention safety of the concave type is higher,so the concave type is better.The test results provide a reliable basis and support for temperature control curve design and optimization of concrete dams.     

Features of a Scan and Clock Resource chip for providing access to board-level test functions

The architecture and some of the specific features of a Scan and Clock Resource (SCR) chip are described. This chip is currently being used in a high-end workstation product to provide access to the testability features of the individual chips and/or printed circuit boards. Using a board-level controller to gain access to the testability features of system components and interfacing the controller to a diagnostics processor (or external tester) is emerging as a common strategy for designing testable digital systems. Based upon experience gained from such an application, controller features that are deemed useful are discussed.This paper is an enhanced version of the author's earlier paper titled Towards a Standard Approach for Controlling Board-Level Test Functions, presented at the IEEE International Test Conference, ITC'90, Washington D.C., September 1990.     

Boundary scan test,test methodology,and fault modeling

The test technique called boundary scan test (BST) offers new opportunities in testing but confronts users with new problems too. The implementation of BST in a chip has become an IEEE standard and users on board level are the next group to begin thinking about using the new possibilities. This article addresses some of the questions about changes in board-level testing and fault diagnosis. The fault model itself is also affected by using BST. Trivial items are extended with more sophisticated details in order to complete the fault model. Finally, BST appears to be a test technique that offers a high degree of detectability on board level, but for diagnosis, some additional effort has to be made.     

Research and Practice of Hybrid Teaching for Software Testing based on Interactive Learning

To address the problems of insufficient number of personalized exercises and cases and teachers' lack of grasp of students' weak knowledge points in the current software testing online courses, we study the strategy of establishing and updating intelligent exercise sets and case libraries and analyze the answers and dig out the weak points of knowledge through group intelligence reasoning and interactive machine learning methods. This will help teachers to make uniform and targeted explanations, reduce manual judgment, and achieve intelligent teaching quality reform, and implement the educational concepts of "keeping up with the times" and "teaching according to students' abilities".     

融入类贡献抑制因子的灰度级模糊C均值图像分割

基于灰度级模糊C均值图像分割算法具有分割速度快的优势。由于无损检测图像中背景类和目标类差异较大,该算法不能有效地将目标分割出来,故提出改进的基于灰度级的模糊C均值算法。构建了一种与类大小反向相关的类贡献抑制因子表达式,将之融入目标函数后能够降低较大类对目标函数的贡献,这可避免较小类的聚类中心受较大类的影响而靠近较大类的聚类中心。最小化新的目标函数可得新形式的隶属度和聚类中心表征形式。采用类大小差异较大的无损检测图像进行试验,结果显示本文算法得到的分割图像视觉效果良好,而且指标G_mean也更高,进一步提升了基于灰度级模糊C均值算法适应能力。     

国产60吨铝熔炉感应式电磁搅拌器的应用

介绍了60t炉底感应式电磁搅拌器的应用方案、工作原理、设备组成和安装形式,阐述了电磁搅拌器对熔融金属化学成分均匀性、温度均匀性以及金相组织的影响,分析了电磁搅拌的整体运行效果,并总结了电磁搅拌器的应用特点。     

液态铝合金表面张力快速检测新方法与装置

表面张力是液态合金的重要物性参数之一,铝合金表面张力与其变质处理效果及充型能力等质量参数密切相关,研究铸造铝合金表面张力快速检测方法及装置,对于开发铝合金熔炼质量炉前实时评价系统具有非常重要的实际意义.介绍了一种液态铝合金表面张力快速测试的新方法和新装置,新方法以固定时间内吹入被测液体的气泡个数以及气泡在生长过程中内部压差变化为信息参数,通过回归公式求解表面张力.基于该方法研制的表面张力新型测试装置由单片机测控单元、探头及其锁紧和升降机构、供气单元等部分构成.采用新装置可在5 s内测得铝合金表面张力,且具有较高的测试精度.     

Ongoing verification of a multiphysics community code: FLASH

When developing a complex, multi‐authored code, daily testing on multiple platforms and under a variety of conditions is essential. It is therefore necessary to have a regression test suite that is easily administered and configured, as well as a way to easily view and interpret the test suite results. We describe the methodology for verification of FLASH, a highly capable multiphysics scientific application code with a wide user base. The methodology uses a combination of unit and regression tests and an in‐house testing software that is optimized for operation under limited resources. Although our practical implementations do not always comply with theoretical regression‐testing research, our methodology provides a comprehensive verification of a large scientific code under resource constraints.Copyright © 2013 John Wiley & Sons, Ltd.     

基于AES算法的存储测试系统设计

为了实现对存储测试系统在某些应用场合中数据保密的需求,提出了一种基于AES算法的数据加密系统设计方案,并完成了系统的算法仿真与硬件设计。系统的硬件以Xilinx公司的FPGA为主要芯片,实现数据采集与加密功能。采用VHDL语言来描述AES算法的硬件实现,对AES加密系统的整体结构和各个子模块进行了仿真与优化。从仿真测试结果看,完全能够满足存储测试系统的加密要求,达到了设计要求。     

AFDX总线10M接口电气参数极限适应性测试方法

AFDX(航空电子全双工交换式以太网)作为新型机载数据总线应用于大中型飞机,其通信接口电气参数的极限适应性测试是一项重要测试内容.提出一种10M标准AFDX总线信号发生器实现方案,采用4路非归零(NRZ)编码模拟双极性差分曼彻斯特编码,产生符合ARINC664规约要求的总线数据信号,并实现数据信号的传输速率、差分信号幅度、上升/下降时间等电气特性参数连续可调,满足AFDX总线10M接口电气参数极限适应性测试需求.