Optical and mechanical properties of jet printed and UV cured blue pixels with phosphated epoxy acrylate as the curing agent

Phosphated epoxy acrylate and phosphated imide-epoxy were synthesized and used as compositions of non-volatile (no solvent) UV curable ink for manufacturing the jet-printed LCD color filter (CF). Phosphated epoxy acrylate oligomer showed not only good solubility in UV curable monomers and pigment compatibility as ink compositions, but also good thermal and mechanical properties after curing. No receiver layer or barrier ribs are necessary to prevent the printed ink from overflowing to the neighboring area. The color inks were precisely ejected to the glass substrate and UV-cured immediately to make the stripe pattern. The printed blue stripes exhibited smooth surface, straight edge, high transparency (transmittance > 84%), high nanoindentation hardness (3.94 GPa) and modulus (72.15 GPa). The influences of curable compositions on the optical properties, patterning properties, surface morphology and nanoindentation hardness of the micro-stripes were discussed.     

Advancements in materials,devices, and integration schemes for a new generation of neuromorphic computers

The slowing pace of performance improvements in modern processors along with the breakdown of power scaling forecasts an imminent end to the traditional transistor scaling roadmap. Additionally, meeting the aggressive demands of proliferating applications in big-data processing, machine learning, artificial intelligence, and highly distributed edge computing requires radical advancements in materials, devices, and architectures for future processors. Neuromorphic computing has emerged as the most promising successor to conventional complementary metal oxide semiconductor (CMOS) devices and von Neumann architecture. This work reviews the status of neuromorphic research, compares the traditional CMOS approach with neuromorphic devices for implementing biologically inspired circuits, and provides an outlook into integration schemes for future brain-inspired computing hardware.     

Epitaxy of BaTiO3 thin film on Si(0 0 1) using a SrTiO3 buffer layer for non-volatile memory application

In this study we report the epitaxial growth of BaTiO₃ films on Si(0 0 1) substrate buffered by 5 nm-thick SrTiO₃ layer using both MBE and PLD techniques. The BaTiO₃ films demonstrate single crystalline, (0 0 1)-oriented texture and atomically flat surface on SrTiO₃/Si template. The electrical characterizations of the BaTiO₃ films using MFIS structures show that samples grown by MBE with limited oxygen pressure during the growth exhibit typical dielectric behavior despite post deposition annealing process employed. A ferroelectric BaTiO₃ layer is obtained using PLD method, which permits much higher oxygen pressure. The C-V curve shows a memory window of 0.75 V which thus enable BaTiO₃ possibly being applied to the non-volatile memory application.     

Ceph分布式存储系统性能优化技术研究综述

Ceph是一个统一的分布式存储系统,可同时提供块、文件和对象3种接口的存储服务。与传统的分布式存储系统不同,它采用了无中心节点的元数据管理方式,因此具有良好的扩展性和线性增长的性能。经过十余年的发展,Ceph已被广泛地应用于云计算和大数据存储系统。作为云计算的底层平台,Ceph除了提供虚拟机的存储服务外,还可以直接提供对象存储服务和NAS文件服务。Ceph支撑着云计算系统中多种操作系统和应用的存储需求,它的性能对其上的虚拟机和应用有较大的影响,因此Ceph存储系统的性能优化一直是学术界和工业界的研究热点。文中首先介绍了Ceph的架构和特性;然后针对现有的性能优化技术,从对内部机制进行改进、面向新型硬件和基于应用的优化这3个方面进行了归纳和总结,综述了近年来Ceph存储和优化的相关研究;最后对该领域未来的工作进行了展望,以期为分布式存储系统性能优化的研究者提供有价值的参考。     

Potentiality of trap charge effects and SiON induced interface defects in a-Si3N4/SiON based MIS structure for resistive NVM device

Potential application of amorphous silicon nitride (a-Si₃N₄)/silicon oxy-nitride (SiON) film has been demonstrated as resistive non-volatile memory (NVM) device by studying the Al/Si₃N₄/SiON/p-Si metal–insulator–semiconductor (MIS) structure. The existence of several deep trap states was revealed by the photoluminescence characterizations. The bipolar resistive switching operation of this device was investigated by current–voltage measurements whereas the trap charge effect was studied in detail by hysteresis behavior of frequency dependent capacitance–voltage characteristics. A memory window of 4.6 V was found with the interface trap density being 6.4 × 10¹¹ cm⁻² eV⁻¹. Excellent charge retention characteristics have been observed for the said MIS structure enabling it to be used as a reliable non-volatile resistive memory device.     

Contactless read-out of printed memory

Contactless read-out of inkjet printed programmable memory is demonstrated. The memory is arranged as a conducting comb pattern consisting of parallel lines adjacent to a common electrode. The information content of the memory is stored in memory bits, which modulate the electrical surface-area of the lines. The data is read-out capacitively by sweeping the tip of a printed circuit board over the memory. The memory bits were printed using silver nanoparticle ink and switched from an initial, high-resistance state to a low-resistance state using rapid electrical sintering, and furthermore, from the low-resistance state to an open-circuit state via fuse-like action. This read-out approach offers potential for low-cost memory applications as well as e.g. resistance-change sensors.     

Silicon nanowire NVM cell using high-k dielectric charge storage layer

Si nanowire (SiNW) channel non-volatile memory (NVM) cells were fabricated by a “self-alignment” process. First, a layer of thermal SiO₂ was grown on a silicon wafer by dry oxidation, and the SiNWs were then grown by chemical vapor deposition in pre-defined locations. This was followed by depositing the gate dielectric, which almost surrounds the nanowire and consists of three stacked layers: SiO₂ blocking layer, HfO₂ charge-storing layer and a thin tunneling oxide layer. Source/drain and gate electrodes were formed by photolithography and lift-off, and the devices were electrically tested. As expected from this fabrication process and the enhanced electrostatic control of the “surrounding” gate, excellent cell characteristics were obtained.     

A low power CMOS compatible embedded EEPROM for passive RFID tag

A 512-bit low-voltage CMOS-compatible EEPROM is developed and embedded into a passive RFID tag chip using 0.18 μm CMOS technology. The write voltage is halved by adopting a planar EEPROM cell structure. The wide Vth distribution of as-received memory cells is mitigated by an initial erase and further reduced by an in-situ regulated erase operation using negative feedback. Although over-programmed charges leak from the floating gates over several days, the remaining charges are retained without further loss. The 512-bit planar EEPROM occupies 0.018 mm² and consumes 14.5 and 370 μW for read and write at 85 °C, respectively.     

Transfer-printed thin film metal electrodes for high-performance ferroelectric P(VDF-TrFE) devices

Electrodes formation method has been found to be very important in electronic devices using ferroelectric P(VDF-TrFE) copolymer. Depending on the deposition system used, vacuum-based deposition methods such as e-beam or thermal evaporation of metal electrodes has resulted in the performance deterioration, due to damages on the fragile organic surface by highly energetic particles such as intensive short-wavelength radiation, secondary electrons, etc. On the other hand, the transfer-printing of electrodes, which is formed on other substrates, onto the organic surface does not involve any such damages, leading to high-performance devices. Further, the transfer-printing process allows additional advantages of electrode surface tailoring or device fabrication on non-flat micro-rough surfaces. The proposed technique has led to much better performance of InGaZnO-based non-volatile memory transistors, compared to devices based on the direct evaporation of metal electrode. Transfer-printing of electrodes, instead of direct vacuum-based deposition, may lead to higher performing devices based on other organic electronic materials.     

Trapping properties of sputtered hafnium oxide films: Bulk traps vs. interface traps

The purpose of this work is to investigate the influence of the spatial distribution of traps on the electrical characteristics of hafnium oxide films deposited by physical vapor deposition. Samples were Al gated metal-oxide-semiconductor capacitors with hafnium oxide films deposited on SiO₂ layer thermally grown on Si. During capacitance-voltage measurements large hysteresis, up to 10 V, are observed in all samples. It is shown that depending on the hafnium oxide deposition conditions, the spatial distribution of the traps responsible for the hysteresis can be either two dimensional (interface/border traps) or three dimensional (bulk traps).