低功耗高性能限流比较器的设计与仿真

为了进一步改善DC-DC开关电源的效率、功耗和精度,以其中最关键的电路:限流电路为突破口,对传统CPM控制结构进行了改进,并引入了动态偏置的思想,采用0.6μmBICMOS工艺模型,设计了一种高性能、低功耗的限流比较器.分析了电路的设计原理和过程,并给出了仿真结果.     

多用户JT MIMO系统下行联合功率分配算法

文中提出一种多用户MIMO下行联合发送（简称JTMIMO）技术中的功率分配算法。首先给出了多用户JT MIMO下行链路模型，并导出了下行信道干扰模型和有偏信道信息下的SINR公式。在此基础上，文中提出一种适用于多用户JTMIMO下行链路的联合功率分配算法，仿真验证表明：通过合理分配用户的发送功率，在满足每个用户信干比（SINR）的前提下，最小化总传榆能量具有较好的能量效率。     

频率抖动技术在开关电源EMC设计中的应用

文章先分析了开关电源的噪声产生原因,然后在研究频率抖动抗干扰理论和EMI测试仪器测试原理的基础上,提出频率抗干扰技术。最后结合某信息类产品的开关电源测试的频谱图,分析了频率抖动技术是如何减小EHI以及该技术本身可能带来的骚扰问题。     

基于压缩量化的非正弦时域正交调制信号预失真方法

针对基于椭圆球面波函数的非正弦时域正交调制信号峰均功率比较高,因而受功率放大器非线性失真影响较大的问题,该文设计了一种基于波形训练的非迭代查询表预失真结构。由于所选量化方法直接决定了查询表预失真器的精度,通过分析调制信号的幅值分布特性,提出一种综合考虑功率放大器特性及信号幅值分布特性的压缩量化方法。对采用所提预失真方法前后信号的带内带外失真特性进行了仿真,并与采用幅度均匀量化方式的性能进行了比较。结果表明,该文方法有效改善了非正弦时域正交调制信号功率谱及系统误码率特性,减小了功率放大器给信号带来的非线性失真。     

智能卡SPA＆DPA攻击

智能卡是一种可防止被入侵设计的设备，为了防止攻击者藉由边际信道泄漏信息，如功率消耗、执行时间、故障时的输出与输入行为、电磁辐射、功率尖峰情形等信息攻击智能卡，必须采取一些防备措施。本文主要介绍攻击智能卡的简易功率分析（SPA），微分功率分析（DPA）。这些技术已被广泛地使用于窃取智能卡保护数据的技术上，提供这些技术的概略性观念，使我们知道问题所在，进一步想出对策，促使我们设计出更安全的智能卡。     

耦合腔行波管功率合成

介绍了脉冲幅相一致耦合腔行波管的研制,并较为详细地介绍和分析了耦合腔行波管功率合成实验--脉冲相位一致性测试的一种途径.     

基于合作中继的OFDM蜂窝网络的QoS感知资源调度算法

针对基于中继的OFDM蜂窝网络,该文考虑具有不同QoS要求的混合业务场景,引入合作传输机制,提出了一种基于合作中继的QoS感知资源调度算法,解决了合作中继节点选取,子载波分配以及功率控制等问题。以最大化系统效用为目标,在考虑QoS业务的速率要求与基站功率约束的同时,针对中继结构引入了中继节点的功率约束。为降低计算复杂度,将原非线性组合优化问题分解为子载波分配与功率控制两个子问题。仿真结果表明,该文所提算法在能量节约、系统效用,吞吐量等性能方面都有显著优势。     

ITECH负载对电源进行老化测试方案

该文详细介绍了ITECH电子负载和老化软件对于电源产品在长时间通电老化试验中的应用,主要结合本系统中的硬件产品和主要的实现监控界面,实现多个电源产品的老化的同时性和自动化性,可以最大程度地发挥电子负载在老化系统中的作用,可以得到准确的监控数据,可最大程度地节约人力成本。该系统已经应用到实际的老化试验中,并在电源等产品的老化中推广和应用。     

Statistical analysis of large on-chip power grid networks by variational reduction scheme

One of the most critical challenges in today's CMOS VLSI design is the lack of predictability in chip performance at design stage. One of the process variabilities comes from the voltage drop variations in on-chip power distribution networks. In this paper, we present a novel analysis approach for computing voltage drops of large power grid networks under process variations. The new algorithm is very efficient and scalable for huge networks with a large number of variational variables. This approach, called variational extended truncated balanced realization (varETBR), is based on model order reduction techniques to reduce the circuit matrices before the variational simulation. It performs the parameterized reduction on the original system using variation-bearing subspaces. After the reduction, Monte Carlo based statistical simulation is performed on the reduced system and the statistical responses of the original system are obtained thereafter. varETBR calculates variational response Grammians by Monte Carlo based numerical integration considering both system and input source variations in generating the projection subspace. varETBR is very scalable for the number of variables and flexible for different variational distributions and ranges as demonstrated in experimental results. Experimental results, on a number of IBM benchmark circuits up to 1.6 million nodes, show that the varETBR can be 1900X faster than the Monte Carlo method and is much more scalable than one of the recently proposed approaches.     

Loosely coupled multi-bit flip-flop allocation for power reduction

Merging 1-bit flip-flops into multi-bit flip-flops in the post-placement stage is one of the most effective techniques for minimizing clock power. In this work, we introduce a new style of multi-bit flip-flop, called loosely coupled multi-bit flip-flop (LC-MBFF). The merit of LC-MBFF is that the logically constituent 1-bit flip-flops in LC-MBFF can be physically apart (i.e., no relocation), providing no need to set aside white space. Utilizing LC-MBFFs, we propose a multi-bit flip-flop allocation algorithm which fully explores the diverse allocation of LC-MBFF structures to maximally reduce clock power consumption. Experimental results with ISCAS89 and IWLS2005 benchmark circuits show that our proposed allocation algorithm using the newly designed multi-bit flip-flops is able to reduce on average the clock power by 8.51% while the best known multi-bit flip-flop allocation algorithm [7] reduces by 5.37%. Additionally, we extend our algorithm to support the multi-bit flip-flop allocation for circuits with clock polarity assignment.