SOI技术的发展及其在航天技术领域的应用

本文简要地综述了多种技术途径制备ＳＯＩ材料的发展现状，并着重讨论了ＳＭＯＸ／ＳＯＩ的潜在优点、发展趋势及其在宇航微电子技术发展中的应用前景．     

SIMOX薄膜上形成钛硅化物的研究

本文报道了在SIMOX(Separation by IMPlanted Oxygen)薄膜材料上制备钛硅化物的研究结果。研究表明,不同厚度的SIMOX薄膜材料上都形成了均匀的TiSi_2,其薄层电阻为4.0—4.5Ω/□,上层Si中的载流子峰值浓度达2×10~(20)/cm~3,获得了一种TiSi_2/n~+-Si/SiO_2/Si的多层结构。形成TiSi_2后,As原子在上层Si中的分布与SIMOX薄膜厚度有关,当上层Si很薄时,As原子在上层Si与SiO_2埋层的界面上的堆积是明显的。     

短沟道CMOS／SIMOX器件与电路的制造

本文简要介绍短沟道ＣＭＯＳ／ＳＩＭＯＸ器件与电路的研制。在自制的ＳＩＭＯＸ材料上成功地制出了沟道长度为１．０μｍ的高性能全耗尽ＳＩＭＯＸ器件和１９级ＣＭＯＳ环形振荡器。Ｎ管和Ｐ管的泄漏电流均小于１×１０－１２Ａ／μｍ，在电源电压为５Ｖ时环振电路的门延迟时间为２８０ｐｓ。     

退火方式和气氛对SIMOX材料质量的影响

本文较为详细地研究了退火程序、退火气氛和注入方式对ＳＩＭＯＸ材料质量的影响，结果表明，采用二重或三重注入并在Ａｒ＋０．５％Ｏ２中退火，可以获得光滑平整的Ｓｉ／ＳｉＯ２界面和高质量的表面硅层。     

Characterization of interface defects in oxygen-implanted silicon films

Defects in ungated n- or p-type and gated p-type resistors have been characterized by photoinduced transient spectroscopy (PITS). These resistors were fabricated with p-type separation by implanted oxygen (SIMOX) wafers with a single-energy 200-keV oxygen implant to a total fluence of 1.8 × 10¹⁸ cm⁻². One wafer, used for gated resistor fabrication was implanted at 595°C and sequentially annealed at 1325°C for 4 h in argon (plus 0.5% oxygen) followed by 4 h in nitrogen (plus 0.5% oxygen). Another wafer, used for ungated resistor fabrication, was implanted at 650°C and annealed at 1275°C for 2 h in nitrogen (plus 0.5% oxygen). The photoconductive response of these resistors to a 1-μs long visible light pulse, measured at temperatures in the 80-to 170-K range, shows different persistent photoconductive effects due to trapped minority carriers that are somewhat linked to the thermal anneal given to the SIMOX wafers. Our results indicate that more damage is present in the wafer annealed at 1275°C than in the one annealed at 1325°C. We model the photoconductive response in terms of a perpendicular built-in field created in the conductive film by trapped charge located at or near the interface with the buried oxide. Defects distributed throughout the conductive film body or located at the interface with the gate oxide are not expected to contribute significantly to the PITS signature, because of the fabrication of the gate oxide with standard metal-oxide semiconductor technology. We estimate the average trap density at the back interface to be in the 10¹¹ cm² range.     

Numerical analysis of silicon-on-lnsulator short channel effects in a radiation environment

Radiation-induced charge build-up in the buried oxide (BOX) of SOI MOSFETs affects device performance through threshold voltage shifts of the back channel. This charge build-up is related to the electric field in the BOX during irradiation. In this paper, we report on the application of a numerical model for the potential distribution in a semiconductor device to the task of determining the electric field in the BOX. This electric field distribution is then combined with a model for charge accumulation as a function of electric field during irradiation to predict the threshold voltage shifts in the back channel of SOI MOSFET devices as a function of channel length. For the device design analyzed here, this model agrees with available experimental data and predicts an increase in back channel threshold shift as the channel length enters the sub-micron regime.     

发展中的SiCOI技术

SiCOI技术是SiC材料与SOI技术结合而形成的一种新的微电子技术，它的产生与发展不仅推动SIC半导体技术的发展，还将弥补SI SOI技术应用的局限性，并将在高温、高频、大功率、抗辐射等电子学领域得到应用的发展。文章介绍了近年来SiCOI技术的最新进展和简要评述。     

总剂量辐射对0.5μm部分耗尽SOI CMOS器件的影响

介绍了基于SIMOX SOI晶圆的0.5μm PD SOI CMOS器件的抗总剂量辐射性能。通过CMOS晶体管的阈值电压漂移,泄漏电流和32位DSP电路静态电流随总剂量辐射从0增加到500 krad(Si)的变化来表现该工艺技术的抗电离总剂量辐射能力。对于H型(无场区边缘)NMOS晶体管,前栅阈值电压漂移小于0.1 V;对于H型PMOS晶体管,前栅阈值电压漂移小于0.15 V;未发现由辐射引起的显著漏电。32位DSP电路在500 krad(Si)范围内,静态电流小于1 m A。通过实验数据表明,在较高剂量辐射条件下,利用该工艺制造的ASIC电路拥有良好的抗总剂量辐射性能。     

A STUDY ON HOT-CARRIER-INDUCED GATE OXIDE BREAKDOWN IN PARTIALLY DEPLETED SIMOX MOSFET’S

The hot-carrier-induced oxide regions in the front and back interfaces are systematic-cally studied for partially depleted SOI MOSFET‘s .The gate oxide properties are investigated for channel hot-carrier effects.The hot-carrier-induced device degradations are analyzed using stress experiments with three typical hot-carrier injection,i.e.the maximum gate current, maximum substrate current and parasitic bipolaf transistor action.Experiments show that PMOSFET‘s degradation is caused by hot carriers injected into the drain side of the gate oxide and the types of trapped hot carrier depend on the bias conditions, and NMOSFET‘s degradation is caused by hot holes.This paper reports for the first time that the electric characteristics of NMOSFET‘s and PMOSFET‘s are significantly different after the gate oxide breakdown, and an extensive discussion of the experimental findings is provided.     

沟道热载流子导致的 PDSOI NMOSFET's击穿特性

对热载流子导致的 SIMOX衬底上的部分耗尽 SOI NMOSFET's的栅氧化层击穿进行了系统研究 .对三种典型的热载流子应力条件造成的器件退化进行实验 .根据实验结果 ,研究了沟道热载流子对于 SOI NMOSFET's前沟特性的影响 .提出了预见器件寿命的幂函数关系 ,该关系式可以进行外推 .实验结果表明 ,NMOSFET's的退化是由热空穴从漏端注入氧化层 ,且在靠近漏端被俘获造成的 ,尽管电子的俘获可以加速 NMOSFET's的击穿 .一个 Si原子附近的两个 Si— O键同时断裂 ,导致栅氧化层的破坏性击穿 .提出了沟道热载流子导致氧化层击穿的新物理机制