太赫兹Si/SiGe量子级联激光器的能带设计

使用nextnano3模拟软件计算Si/Si1-xGex/Si量子阱的能带结构,对Si/SiGe量子级联激光器有源区的能带结构进行设计,结果表明使用Ge组分为0.27～0.3,量子阱宽度为3nm的SiGe合金与垒宽为3nm的Si层构成对称应变级联异质结构,有利于优化THz Si/SiGe量子级联激光器结构.     

UHV/CVD生长本征硅外延层的研究

在微波双极型晶体管中,收集区的厚度是影响其截止频率的一个重要因素。普通的常压外延难以生长出杂质浓度变化陡峭的薄外延层。文章利用自行研制的超高真空化学气相淀积(UHV/CVD)系统SGE500,在N型(掺As)重掺杂衬底上进行了薄本征硅外延层生长规律的研究;并采用扩展电阻(SPR)、原子力显微镜(AFM)、双晶衍射(DCXRD)等方法,对外延层的质量进行了评价。采用该外延材料制作的锗硅异质结双极型晶体管(SiGe HBT)器件击穿特性良好。     

一种5位10 GHz SiGe BiCMOS比较器

SiGe BiCMOS提供了性能极其优异的异质结晶体管(HBT),其ft超过70 GHz,β>120,并具有高线性、低噪声等特点,非常适合高频领域的应用。基于SiGe BiCMOS工艺,提出了一种高性能全差分超高速比较器。该电路由宽带宽前置放大器和改进的主从式锁存器组成,采用3.3 V单电压源,比较时钟超过10 GHz,差模信号电压输入量程为0.8 V,输出差模电压0.4 V,输入失调电压约2.5 mV;工作时钟10 GHz时,用于闪烁式A/D转换器可以达到5位的精度。     

重掺杂P型Si1-xGex层中少数载流子浓度的低温特性

考虑了重掺杂引起的禁带变窄效应,建立起少数载流子室温和低温模型,并进行了定量的计算。研究发现,p-Si1-xGex中的少子浓度(电子)随x的增加而增加。在重掺杂条件下,常温时,少子浓度随杂质浓度的上升而下降;而低温时,少子浓度却随杂质浓度的上升而上升。     

A 2.4 GHz power amplifier in 0.35μm SiGe BiCMOS

This paper presents a 2.4 GHz power amplifier(PA) designed and implemented in 0.35μm SiGe BiCMOS technology.Instead of chip grounding through PCB vias,a metal plate with a mesa connecting ground is designed to decrease the parasitics in the PCB,improving the stability and the gain of the circuit.In addition,a low-pass network for output matching is designed to improve the linearity and power capability.At 2.4 GHz,a P_(1dB) of 15.7 dBm has been measured,and the small signal gain is 27.6 dB with S_(11)<-7 ...     

A 2.1-6 GHz SiGe BiCMOS low-noise amplifier design for a multi-mode wideband receiver

正A wideband low-noise amplifier(LNA) with ESD protection for a multi-mode receiver is presented.The LNA is fabricated in a 0.18-μm SiGe BiCMOS process,covering the 2.1 to 6 GHz frequency band.After optimized noise modeling and circuit design,the measured results show that the LNA has a 12 dB gain over the entire bandwidth, the input third intercept point(IIP3) is -8 dBm at 6 GHz,and the noise figure is from 2.3 to 3.8 dB in the operating band.The overall power consumption is 8 mW at 2.5 V voltage supply.     

应力技术改善CMOS器件性能研究进展

随着集成电路技术的快速发展,等比例缩小技术已经不能满足摩尔定律,应变硅金属氧化物硅场效应晶体管(MOSFET)技术成为后硅时代研究的热点。应变硅技术通过拉伸或压缩硅晶格达到器件尺寸不变的情况下,可提高器件性能的目的,同时应变硅技术与传统硅工艺兼容,节约了生产成本。对于应变硅互补金属氧化物硅晶体管(CMOS)器件的性能以及可靠性问题的研究也日益增加。本文通过介绍几种常用的应变技术(应力记忆技术(SMT),锗化硅技术(SiGe),接触孔刻蚀阻挡层(CESL))的应变机理、材料性能和工艺条件对应力技术的影响来探讨以后应力技术的发展趋势。     

Performance analysis of SiGe double-gate N-MOSFET

The major purpose of this paper is to find an alternative configuration that not only minimizes the limitations of single-gate (SG) MOSFETs but also provides the better replacement for future technology. In this paper, the electrical characteristics of SiGe double-gate N-MOSFET are demonstrated and compared with electrical characteristics of Si double-gate N-MOSFET. Furthermore, in this paper the electrical characteristics of Si double-gate N-MOSFET are demonstrated and compared with electrical characteristics of Si single-gate N-MOSFET. The simulations are carried out for the device at different operational voltages using Cogenda Visual TCAD tool. Moreover, we have designed its structure and studied both I_d-V_g characteristics for different voltages namely 0.05, 0.1, 0.5, 0.8, 1 and 1.5 V and I_d-V_d characteristics for different voltages namely 0.1, 0.5, 1 and 1.5 V at work functions 4.5, 4.6 and 4.8 eV for this structure. The performance parameters investigated in this paper are threshold voltage, DIBL, subthreshold slope, GIDL, volume inversion and MMCR.     

SiGe HBT射频噪声模型研究

对现代的双极型晶体管而言,载流子在基极和集电极的空间电荷区（CB SCR）传输延迟可比基极渡越时间,甚至要大于后者。为了更精确地表征了SiGe HBT的射频噪声性能,对van Vliet模型做了扩展,使其包含基极集电极空间电荷区的延迟效应。用2个与噪声相关的延迟时间对transport模型进行了扩展,使得在没有非准静态Y参数的情况下仍然可以对基极和集电极电流噪声进行精确建模。最后,在JC=12.2 mA/μm2,AE=0.12×18μm2条件下,分别对2种模型的基极和集电极噪声电流谱及其归一化相关系数做图并与计算得出的解析值相比较,验证了模型的有效性。     

High mobility strained Si0.5Ge0.5/SSOI short channel field effect transistors with TiN/GdScO3 gate stack

Short channel p-type metal-oxide-semiconductor field effect transistors (MOSFETs) with GdScO₃ gate dielectric were fabricated on a quantum well strained Si/strained Si_0.5Ge_0.5/strained Si heterostructure on insulator. Amorphous GdScO₃ layers with a dielectric constant of 24 show small hysteresis and low density of interface states. All devices show good performance with a threshold voltage of 0.585 V, commonly used for the present technology nodes, and high I_on/I_off current ratios. We confirm experimentally the theoretical predictions that the drive current and the transconductance of the biaxially strained (1 0 0) devices are weakly dependent on the channel orientation. The transistor’s hole mobility, extracted using split C-V method on long channel devices, indicates an enhancement of 90% (compared to SiO₂/SOI transistors) at low effective field, with a peak value of 265 cm²/V s. The enhancement is however, only 40% at high electrical fields. We demonstrate that the combination of GdScO₃ dielectric and strained SiGe layer is a promising solution for gate-first high mobility short channel p-MOSFETs.