SiGe HBT发射极台面湿法腐蚀技术研究

在SiGeHBT的制造工艺中,为了防止干法刻蚀发射极台面对外基区表面造成损伤,从而导致SiGeHBT小电流下较大漏电问题,对SiGeHBT发射极台面的湿法腐蚀技术进行了研究。通过改变超声功率、腐蚀液温度,从中获得了较为理想的腐蚀条件。     

应变SiGe沟道pMOSFET的击穿特性

以半导体器件二维数值模拟程序Medici为工具,模拟和对比了SiGepMOS同SipMOS的漏结击穿电压随栅极偏压、栅氧化层厚度和衬底浓度的变化关系;研究了SiGepMOS垂直层结构参数硅帽层厚度、SiGe层厚度及Ge剂量和p+ δ掺杂对于击穿特性的影响.发现SiGepMOS击穿主要由窄带隙的应变SiGe层决定,击穿电压明显低于SipMOS并随Ge组分增加而降低;SiGe/Si异质结对电场分布产生显著影响,同SipMOS相比电场和碰撞电离具有多峰值分布的特点;Si帽层及SiGe层参数对击穿特性有明显影响,增加p型δ掺杂后SiGepMOS呈现穿通击穿机制     

pnp型SiGe HBT的制备研究

从pnp型Si/SiGe HBT的能带结构出发，阐述pnp型Si/SiGe HBT的较大原理，采用MBE方法生长Si/Si1-xGex合金材料，并对Si/Si1-xGex合金材料的物理特性和异质结特性进行表征，在重庆固体电子研究所工艺线上，研制出了pnp型Si/SiGe HBT器件，器件参数为：Vcb0=9V,Vcc0=2.5V,Veb0=5V,β＝10。     

pnp型SiGe HBT特性与Ge组分分布的相关性

在进行pnp型SiGe HBT的设计时,通过改变基区Ge组分改变能带结构,从而获得较高的电流增益和截止频率。本文就基区中Ge组分分布的三种形式:三角形、梯形、矩形进行计算机模拟并对结果进行讨论,发现其他条件相同时,梯形分布的pnp SiGe HBT的放大系数最大,而且梯形和三角形随Ge组分的增大而增大,但是矩形分布在Ge组分增大到一定数值后开始减小,而特征频率情况类似。     

调制掺杂层在SiGe PMOSFET中的应用

在普通Si器件性能模拟的基础上，详细研完了长沟应变SiGe器件的模拟，并进一步探讨了调制掺杂层的引入对器件性能(主要是跨导)的影响。在器件模拟过程中，采用隐含的SiGe材料和Si材料模型会得到与实际情况差别较大的结果。根据前人的材料研完工作，引入了插值所得的近似因子，以修正Silvaco中隐含的SiGe能带模型和迁移率参数。然后，依据修正后的模型对SiGe PMOS进行了更为精确的二维模拟，并验证了调制掺杂层的作用。     

Fabrication of strained Si channel PMOSFET on thin relaxed Si1−xGex virtual substrate

A novel MBE-grown method using low-temperature Si technology is introduced into the fabrication of strained Si channel PMOSFETs. The thickness of relaxed Si_1−xGe_x epitaxy layer on bulk silicon is reduced to approximate 400 nm (x=0.2). The Ge fraction and relaxation of Si_1−xGe_x film are confirmed by DCXRD (double crystal X-ray diffraction) and the DC characteristics of strined Si channel PMOSFET measured by HP 4155B indicate that hole mobility μ_p has an maximum enhancement of 25% compared to similarly processed bulk Si PMOSFET.     

突变反型异质结及其双极晶体管的研制

文章对突变反型异质结的能带图、接触电势差和势垒区宽度进行了讨论和研究。同时，介绍了基于分子束外延(MBE)法生长的SiGe／Si结构的异质结双极晶体管(HBT)制造工艺，并给出了测试结果。     

SiGe共振腔增强型探测器的制备

利用SOI材料的埋层二氧化硅的自停止特性,成功制作了具有高反射底镜的共振腔增强型SiGe探测器.底镜沉积于EPW腐蚀液腐蚀形成的背孔内,在1.2～1.5μm范围内,反射率高达99%.探测器的共振峰在1.344μm,光响应为1.2mA/W.与普通结构的探测器相比,文中所报道的探测器光响应有8倍的增强.     

基于SiGe量子点实现增强F-N隧穿的低压闪速存储器

提出了一种用于半导体闪速存储器单元的新的Si/SiGe量子点/隧穿氧化层/多晶硅栅多层结构,该结构可以实现增强F-N隧穿的编程和擦除机制.模拟结果表明该结构具有高速和高可靠性的优点.测试结果表明该结构的工作电压比传统NAND结构的存储器单元降低了4V.采用该结构能够实现高速、低功耗和高可靠性的半导体闪速存储器.     

Titanium silicide/germanide formation on submicron features for high mobility SiGe channel field effect transistors

The formation of self-aligned Ti(Si_(1−x)Ge_(x))₂ on submicron lines is described. The silicide/germanide is formed by reacting sputtered Ti with epitaxially grown Si_(1−x)Ge_(x) of composition and thickness relevant to high mobility Si_(1−x)Ge_(x) channel field effect transistors. Ti(Si_(1−x)Ge_(x))₂ formation on narrow lines was carried out on phosphorous doped material, because of the well known difficulties of forming silicide on heavily n-doped silicon. A companion set of boron doped blanket films was also processed. The results show that the process temperature required for the minimization of silicide/germanide sheet resistance is reduced as compared to silicide formation on Si alone. However, the silicide/germanide films agglomerate with increased high temperature processing more easily than pure silicide. The thermal stability is degraded more for films with higher Ge content and is a strong function of dopant type. Silicide/germanide formation on phosphorous doped Si_(1−x)Ge_(x) layers with x = 10% have a line width dependence similar to silicide formation. Formation on phosphorous doped Si_(1−x)Ge_(x) layers with x = 27% display an inverse line width dependence, with higher overall sheet resistance. Formation of silicide/germanide on blanket films of boron doped Si_(1−x)Ge_(x) with x = 27% behaved similar to the formation of silicide on silicon.