日产NHR-90W型催化剂失活原因分析

对日产NHR -90W催化剂在抚顺石化分公司石油二厂 6万t/a石蜡加氢装置运行情况进行了研究 ,证明该催化剂活性较高 ,对原料的适应性也较强。同时 ,对造成催化剂短期内失活的原因进行了分析 ,认为原料中铁离子含量过高是造成催化剂失活的主要原因。对相关装置生产控制提出了建议     

CAD/CAM在注射模设计中的应用

以Pro/E、Moldflow软件为例,对CAD/CAM技术在注射模设计中的应用进行了研究和探讨,总结了使用该软件的一些体会,阐述了注射模CAD/CAM技术的发展趋势。     

十二酰胺丙基二甲基羟乙基氯化铵与十二烷基硫酸钠水溶液的表面吸附和胶束形成

利用十二酰胺丙基二甲胺和氯乙醇反应 ,合成了十二酰胺丙基二甲基羟乙基氯化铵 (DDHA)阳离子表面活性剂 ,将其与十二烷基硫酸钠 (SDS)以不同摩尔比进行混合 ,测定了混合系统的表面张力 ,计算了单一系统和混合系统的饱和吸附量、分子最小截面积 ,表面层和胶束中 DDHA的摩尔分率及分子间相互作用参数 ,目视观察了混合系统的浑浊情况。结果表明 :在降低γcmc和 cmc方面 ,DDHA SDS混合系统有协同效应 ,表面层和胶束的组成与二组分配比有关 ,但是非对称的 ,等物质的量混合物中 ,DDHA在胶束和表面层中具有较大的摩尔分数。DDHA与 SDS在实验测定的各混合系统中都不出现混浊     

光漂白法制备有机聚合物非线性定向耦合器

研究了用光漂白的方法制备PMMA/DR1聚合物非线性定向耦合器,提出了一种容易的制备方法来得到要求的耦合长度.测量了材料的光学非线性对定向耦合器两臂透过率的影响.实验结果表明由于光学非线性,耦合器的耦合长度随着入射光强度的改变而发生变化.     

Intermetallic compounds formed at the interface between liquid indium and copper substrates

The interfacial reactions between liquid In and Cu substrates at temperatures ranging from 175°C to 400°C are investigated for the applications in bonding recycled sputtering targets to their backing plates. Experimental results show that a scallop-shaped Cu₁₆In₉ intermetallic compound is found at the Cu/In interface after solder reactions at temperatures above 300°C. A double-layer structure of intermetallic compounds containing scallop-shaped Cu₁₁In₉ and continuous CuIn is observed after the Cu/In interfacial reaction at temperatures below 300°C. The growth of all these intermetallic compounds follows the parabolic law, which implies that the growth is diffusion-controlled. The activation energies for the growth of Cu₁₆In₉, Cu₁₁In₉, and CuIn intermetallic compounds calculated from the Arrhenius plot of growth reaction constants are 59.5, 16.9, and 23.5 kJ/mole, respectively.     

DCS在50MW供热机组上的应用

介绍I/A’S系统在巨化热电厂八号50MW供热机组上应用实例,并从DCS系统的整体设计到实现的功能、控制效果等多方面进行了分折,总结了调试和运行经验。     

On the existence and synthesis of multifinger positive grips

We study the criteria under which an object can be gripped by a multifingered dexterous hand, assuming no static friction between the object and the fingers; such grips are calledpositive grips. We study three cases in detail: (i) the body is at equilibrium, (ii) the body is under some constant external force/torque, and (iii) the body is under a varying external force/torque. In each case we obtain tight bounds on the number of fingers needed to obtain grip.We also present efficient algorithms to synthesize such positive grips for bounded polyhedral/polygonal objects; the number of fingers employed in the grips synthesized by our algorithms match the above bounds. The algorithms run in time linear in the number of faces/sides.The paper may be of independent interest for its presentation of algorithms arising in the study of positive linear spaces.Work on this paper has been supported by Office of Naval Research Grant N00014-82-K.-0381, National Science Foundation Grant No. NSF-DCR-83-20085, and by grants from the Digital Equipment Corporation, and the IBM Corporation.     

基于FAX／40E电话语音／传真卡的通信技术研究

以一个基于 FAX/ 40 E电话语音 /传真卡技术的传真系统为例 ,重点研究 FAX/ 40 E电话语音 /传真卡技术与计算机之间的通信技术 ,并讨论有关多线程技术问题。     

I/OIMAGESYSTEM微波中继应用

微波中继的应用非常广泛 ,目前在二维、三维施工中跨越障碍物时 ,一般都使用微波中继站来传输命令和数据。文章就微波中继及I/OIMAGESYSTEM“蛇形排列”先进功能的实际应用进行了详细的阐述 ,同时提出了使用微波中继站应注意的问题。     

CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.