黑白电视机的电磁兼容设计

本文结合我厂μPC三片机的设计布局,探讨黑白电视机电路的电磁兼容设计。通过理论计算,提出中放屏蔽材料选择的理论依据。     

球面端面抛物型发散GRIN透镜的光束光学理论

本文基于高斯光束传播理论,研究高斯光束经端面为球面的抛物型发散梯度折射率纤维透镜的变换特性,结果可用于梯度折射率激光束变换元件的设计。     

辅助沉积线状(3×20cm)离子源设计

线状离子源适合于大面积材料的连续溅射改性过程。多极场设计技术在3×20cm线状离子源的放电室中有很好的应用。     

梯度折射率纤维端面耦合成像元件的设计

根据抛物型梯度折射率纤维透镜的近轴成像公式,分析了具有一定缩放倍率的梯度折射率纤维端面耦合成像的特性,探讨了这种纤维端面耦合成像元件的设计。     

循环移位可编程序逻辑阵列的可测试性设计

本文研究了一种“芯片内部自测式”可编程序逻辑阵列(Built-in Sclf Tcst PLA)的设计方法:循环移位PLA(简称CS-PLA)法.CS-PLA与其他PLA可测试性设计方法相比,具有故障覆盖率高、对电路速度影响小、测试生成简单等特点,当PLA嵌入在芯片内部时,不需要单独的测试状态。其芯片面积成本随PLA的规模增大而降低,因此CS-PLA特别适用于大规模“嵌入式”PLA.     

电子电路噪声的岔集谱分析法

本文阐明了目前电路噪声理论的不完善性,提出了电子电路岔集谱分析法,使噪声计算的精度和效率有显著提高。作者编制并调试成功了基于此方法的电子电路噪声性能分析和低噪声设计程序,文末给出了实例结果。与实验结果的比较,说明了本文提出方法的正确性。     

非平面接地静磁表面波延迟线的优化设计＊

本文改进了非平面接地静磁表面波延迟线器件模型,并首次采用递归二次规划对器件结构进行了优化设计,为静磁波器件设计提供了新途径。     

光伏MPPT系统电压控制器的优化设计

分析了光伏MPPT系统构成及工作原理。使用基于变步长电压扰动法作为功率/电压寻优控制器。为实现快速稳定的光伏MPPT响应,重点对光伏输出电压控制器的电压环进行优化设计。设计了一种光伏MPPT电压复合控制器,采用电压顺馈+PI调节器的方法实现。通过对光伏输出电压控制器进行数学建模得到电压闭环传递函数。确定了最佳PI调节器参数以得到快速稳定的MPPT控制。仿真分析结果以及试验结果表明,此电压复合控制器能够快速、稳定地实现光伏MPPT响应。     

Partial scan flip-flop selection by use of empirical testability

Partial serial scan as a design for testability technique permits automatic generation of high fault coverage tests for sequential circuits with less hardware overhead and less performance degradation than full serial scan. The objective of the partial scan flip-flop selection method proposed here is to obtain maximum fault coverage for the number of scan flip-flops selected. Empirical Testability Difference (ETD), a measure of potential improvement in the testability of the circuit, is used to successively select one or more flip-flops for addition or deletion of scan logic. ETD is calculated by using testability measures based on empirical evaluation of the circuit with the acutal automatic test pattern generation (ATPG) system. In addition, once such faults are known, ETD focuses on the hard-to-detect faults rather than all faults and uses heuristics to permit effective selection of multiple flip-flops without global optimization. Two ETD algorithms have been extensively tested by using FASTEST ATPG [1, 2] on fourteen of the ISCAS89 [3] sequential circuits. The results of these tests indicate that ETD yields, on average, 35% fewer uncovered detectable faults for the same number of scanned flip-flops or 27% fewer scanned flip-flops for comparable fault coverage relative to cycle-breaking methods.This work was performed while the author was with the University of Wisconsin-Madison.     

Design of testable sequential circuits by repositioning flip-flops

This paper presents a technique to enhance the testability of sequential circuits by repositioning flip-flops. A novel retiming for testability technique is proposed that reduces cycle lengths in the dependency graph, converts sequential redundancies into combinational redundancies, and yields retimed circuits that usually require fewer scan flip-flops to break all cycles (except self-loops) as compared to the original circuit. Our technique is based on a new minimum cost flow formulation that simultaneously considers the interactions among all strongly connected components (SCCs) of the circuit graph to minimize the number of flip-flops in the SCCs. A circuit graph has a vertex for every gate, primary input and primary output. If gatea has a fanout to gateb, then the circuit graph has an arc from vertexa to vertexb. Experimental results on several large sequential circuits demonstrate the effectiveness of the proposed retiming for testability technique in reducing the number of partial scan flip-flops.