可拆卸低阻抗S2 激光管结构的改进

介绍了可拆卸低阻抗S2激光器的总体设计原则，并给出了几个主要部件的设计，最后对几个重要参数进行了估算。     

红外导引头光学系统的抗干扰设计

文章详细地介绍了某红外导引头所采用的折反式光学系统,并对红外光学系统中产生 的干扰进行了深入的分析与讨论。在此基础上,提出了合理的抗干扰措施,通过对红外导引头光学系统进行光机一体化,进一步提高了系统的总体性能。试验结果表明:该系统有着良好的抗干扰性能,满足总体性能指标要求。     

Ring Network Design by Lagrangean Based Column Generation

We discuss the problem of designing a telecommunication network with the survivability requirement that the network should be composed of connected rings of links. The network design problem is then to choose links from a given network, and compose them into a number of rings. Furthermore, the rings should be connected at certain transit nodes. The traffic between rings may pass through other rings. Each ring is associated with a certain fixed cost depending on the length of the ring. We describe the problem, modeled as a linear integer programming problem, and a heuristic solution method, based on column generation and Lagrangean relaxation.     

Generation of Technology-Independent Retargetable Analog Blocks

This paper introduces a complete methodology for retargeting of analog cells to different sets of specifications. This methodology is technology-independent, thus allowing the migration, from one technology to another, of the circuit under retargeting. Careful integration of the device sizing and layout generation tasks via the incorporation of layout constraints during the sizing process allows to generate fully functional designs in a few minutes. The methodology is illustrated via the retargeting of a fully-differential Miller-compensated two-stage operational amplifier for a new set of specifications and two different technological processes.An erratum to this article can be found at     

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

Low-Power Adaptive Biased Integrated Amplifiers

In this paper the author will present the working principle and the applications of a novel adaptive biasing topology, designed to decrease the stand-by power dissipation without affecting the transient performance of low-power amplifiers. The proposed circuit, whose principle and circuit topology can be implemented both in CMOS and in bipolar standard technologies, gives a biasing current whose value depends on the applied input differential voltage and can be set according to the requested transient performance constraints. The adaptive architecture can be utilized in the design of high-efficient low-power operational amplifiers, for the biasing of both the input stage (where the input source current is dynamically increased) and the output stage (where the output current can be controlled and limited). These amplifiers show a very good behaviour, evaluated in terms of two efficiency factors, if compared with those of other adaptive solutions and class-AB topologies, proposed in the literature. Simulation results and also measurements on a chip prototype, fabricated in a standard CMOS technology, are finally presented.     

单片微型机测控系统的可靠性设计

单片微型机控制系统的可靠性是由多种因素决定的，其中系统硬件的抗干扰性是决定系统可靠性的重要方面。为提高单片机系统的抗干扰能力．使产品能适应恶劣的工作环境，满足可靠性方面更高标准的要求，设计用户系统时应尽量采用可靠性措施。但是，由于实际控制系统千差万剐，干扰源也不尽相同。因此，设计用户系统时应分剐考虑。通过分析单片微型机控制系统在实际应用中存在的3条主要干扰渠道：空间干扰、过程通道干扰和供电系统干扰，然后针对相应情况给出了一些解决措施。重点讨论了软件和硬件相结合的解决方案和简单看门狗电路的设计。     

针对多方参与特征的地理空间信息网格结构设计

地理空间信息网格结构层次设计既考虑了多方参与特征，又参考了目前较为流行的五层沙漏结构和开放网格服务结构，还参考了我国学者从开发的角度提出的一般网格层次结构，以此为基础试设计并探讨地理空间信息网格的基本层次结构。     

电容式高分子湿敏元件的研究及进展

介绍了电容式高分子湿敏元件的几个组成部分一下电极、湿敏功能材料、上电极工艺制造技术。同时也介绍了湿敏元件防污染、电路一体化设计、长期稳定性等方面近来的研究成果。指出湿敏元件的感湿材料的选择和上电极工艺制造技术是影响湿敏元件性能的两个重要因素。     

基于MVC模式的Struts框架的研究

Struts是当前Web应用开发中最为流行的框架之一。介绍了MVC(Model／View／contmller)设计模式和Struts框架的工作原理，在介绍MVC模型的基础上，介绍基于struts的应用软件开发用框架的体系结构，以及基于struts的开发流程。介绍了Stmts实现MVC模式Web应用的开发过程中的一些经验。