Study of dielectric properties of particulate blends

The effect of the addition of high abrasion furnace (HAF) black on the dielectric properties of poly (ethylene‐propylene‐diene monomer) EPDM, polyethylene (PE) blend using both sulphur and peroxide vulcanizing systems was studied. It was observed that the increase in the permittivity is more pronounced with HAF black in the case of sulphur system than for the peroxide one. Many theories have been tested to calculate the effective permittivity of these particulate blends. The observed values of the permittivities are in close agreement with those calculated by Tsangaris's model, taking into account the variation of the aspect ratio (a/b) of the HAF black with the volume fraction of the HAF black in the matrix and type of the vulcanizing system. © 2000 John Wiley & Sons, Inc. J Appl Polym Sci 77: 1816–1821, 2000     

高介电常数、低介电损耗聚合物复合电介质材料研究进展

高介电常数聚合物电介质材料作为当今信息功能材料的研究热点,具有实际的应用价值和前景。综述了聚合物基复合电介质材料的分类及优缺点,以及从材料微观结构设计和填料界面修饰出发(如三元杂化或设计核壳和三明治结构),来获得高介电常数、低介电损耗聚合物复合电介质材料的研究状况和应用前景,以期对高介电、低损耗聚合物基电介质材料有一个更直观全面的了解,进一步拓展该类材料在电气和生物工程领域的研究和应用。     

HfO2 Gate Dielectrics for Future Generation of CMOS Device Application

Introduction High- k gate dielectrics have been extensivelystudied as alternates to conventional gate oxide( Si O2 ) due to the aggressive downscaling of Si O2thickness in CMOS devices,and hence the exces-sive gate leakage.Hf O2 has emerged as one...     

Gate Current Modeling and Optimal Design of Nanoscale Non-Overlapped Gate to Source/Drain MOSFET

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behaviour of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.     

Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks

The decreasing feature sizes in complementary metal-oxide semiconductor (CMOS) transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant (high-k) because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability.In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology.Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties.It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling.In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices.Therefore, detailed atomicscale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks,are highly required.In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed.Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy (HRTEM) and the related techniques based on scanning transmission electron microscopy (STEM), including high-angle annular darkfield (HAADF) imaging (also known as Z-contrast imaging), electron energy-loss spectroscopy (EELS), and energy dispersive X-ray spectroscopy (EDS), due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices.In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics.In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed.The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4.Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.     

原子层淀积制备金属氧化物薄膜研究进展

原子层淀积(ALD)技术作为一种先进的薄膜制备方法近年来越来越得到重视,它能精确地控制薄膜的厚度和组分,实现原子层级的生长,生长的薄膜具有很好的均匀性和保形性,因而在微电子和光电子等领域有广泛的应用前景。本文综述了ALD技术的基本原理,及其在金属氧化物薄膜制备上的研究进展。     

具有低噪声及高线性度的高性能MOCVD-SiNx/AlN/GaN 毫米波MIS-HEMTs

文章在超薄势垒AlN/GaN异质结构上采用金属有机化学气相沉积（MOCVD）原位生长SiN_x栅介质,成功制备了高性能的SiN_x/AlN/GaN金属-绝缘体-半导体高电子迁移率晶体管（MIS-HEMTs）。深能级瞬态谱（DLTS）技术测试SiN_x/AlN的界面信息,显示其缺陷能级深度为0.236 eV,俘获截面为3.06×10^-19 cm^-2,提取的界面态密度为10¹⁰~10¹² cm^-2eV^-1,表明MOCVD原位生长的SiN_x可以有效降低界面态。同时器件表现出优越的直流、小信号和噪声性能。栅长为0.15 μm的器件在2 V的栅极电压（V_gs）下具有2.2 A/mm的最大饱和输出电流,峰值跨导为506 mS/mm,最大电流截止频率（f_T）和最大功率截止频率（f_MAX）分别达到了65 GHz和123 GHz,40 GHz下的最小噪声系数（NF_min）为1.07 dB,增益为 9.93 dB。V_ds = 6 V时对器件进行双音测试,器件的三阶交调输出功率（OIP3）为32.6 dBm,OIP3/P_dc达到11.2 dB。得益于高质量的SiN_x/AlN界面,SiN_x/AlN/GaN MIS-HEMT显示出了卓越的低噪声及高线性度,在毫米波领域具有一定的应用潜力。     

Si versus Ge for future microelectronics

The quest for higher performance of scaled down technologies resulted in the use of high-mobility substrates and strain engineering approaches. The development of advanced processing modules, based on low temperature processing and deposited (MBE, ALD, epitaxially grown, etc.) gate stacks, has triggered the interest of exploring Ge for sub 32 nm technology nodes. A comparison between Si and Ge for future microelectronics has to take into account a variety of materials, processing and performance aspects. Here special attention will be given to passivation and gate stack formation in relation to device performance, including leakage current and reliability aspects. The potential of Ge-based device structures and the monolithic integration of Ge and III-V devices on silicon are highlighted.     

rf-Magnetron sputter deposited ZrO2 dielectrics for metal-insulator-semiconductor capacitors

ZrO₂ gate dielectric thin films were deposited by radio frequency (rf)-magnetron sputtering, and its structure, surface morphology and electrical properties were studied. As the oxygen flow rate increases, the surface becomes smoother. The experimental results indicate that a high temperature annealing is desirable since it improves the electrical properties of the ZrO₂ gate dielectric thin films by decreasing the number of interfacial traps at the ZrO₂/Si interface. The carrier transport mechanism is dominated by the thermionic emission.