一款紧凑增强型可变阻抗电磁带隙结构

基于传统AI-EBG结构,提出了一种小尺寸的增强型电磁带隙结构,实现了从0.5~9.4 GHz的宽频带-40 dB噪声抑制深度,且下截止频率减少到数百MHz,可有效抑制多层PCB板间地弹噪声。文中同时研究了EBG结构在高速电路应用时的信号完整性问题,使用差分信号方案可改善信号完整性。     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

The day of the week when you were born in 700 ms: Calendar computation in an autistic savant.

Some individuals are able to determine the weekday of a given date in a few seconds (finding for instance that June 12, 1900, was a Tuesday). This ability has fascinated scientists for many years because it is predominantly observed in people with limited intelligence and may appear very early in life. Exceptional visual memory, exceptional concentration abilities, or privileged access to lower levels of information not normally available through introspection have been advanced to explain such phenomena. In the present article, the authors show that a simple cognitive model can explain all aspects of the performance of Donny, a young autistic savant who is possibly the fastest and most accurate calendar prodigy ever described. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

数字储频及其性能分析

文章介绍了3种宽带数字储频的基本结构，分析了宽带数字储频的一个重要指标——量化噪声，根据输出信号频谱的杂散电平比较了三种结构的优劣。     

Performance discrepancies on the California Verbal Learning Test-Second Edition (CVLT-II) in the standardization sample.

The standardization data for the California Verbal Learning Test-Second Edition (CVLT-II; D. C. Delis, J. H. Kramer, E. Kaplan, & B. A. Ober, 2000) were used to evaluate the base rate of 6 specific discrepancies between various key variables. The results indicated that CVLT-II performance discrepancies should equal or exceed 1 or 1.5 z score points (depending on the individual comparison) in the hypothesized direction to be considered potentially unusual. However, because about 1 in 3 persons in the standardization sample displayed at least 1 such large discrepancy, it is concluded that these base rates should be viewed only as a starting point for interpretation. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

Cued recall from image and sentence memory: A shift from episodic to identical elements representation.

The applicability of the identical elements (IE) model of arithmetic fact retrieval (T. C. Rickard, A. F. Healy, & L. E. Bourne, 1994) to cued recall from episodic (image and sentence) memory was explored in 3 transfer experiments. In agreement with results from arithmetic, speedup following even minimal practice recalling a missing word from an episodically bound word triplet did not transfer positively to other cued recall items involving the same triplet. The shape of the learning curve further supported a shift from episode-based to IE-based recall, extending some models of skill learning to cued recall practice. In contrast with previous findings, these results indicate that a form of representation that is independent of the original episodic memory underlies cued-recall performance following minimal practice. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

铁电存储器的研究进展

介绍了铁电存储器的存储原理,同时对两种铁电存储器(铁电随机存取存储器和铁电场效应晶体管存储器)的研究进展、当前存在的问题以及我国目前在这一领域的研究现状进行了简单介绍,并对今后的技术发展进行了展望。     

嵌人式与独立存储器设计上的差异分析和研究

进入21世纪,随着集成电路的发展,SoC(System on Chip)片上系统应运而生。而作为SoC重要组成部分的嵌入式存储器,在SoC中所占的比重正逐步增加,并起着越来越重要的作用,那么嵌入式存储器与独立的存储器芯片在设计上存在着哪些差异?对此本文将以NOR型闪存为例在制造工艺的选取、衍生产品的设计、功耗与噪声、后端功能仿真、测试与修复等方面进行分析和研究。     

Flash器件中氧化硅/氮化硅/氧化硅的特性

对普遍采用的氧化硅/氮化硅/氧化硅( ONO)三层复合结构介质层的制备工艺及特性进行了研究分析,研究了ONO的漏电特性以及顶氧( top oxide)和底氧( bottom oxide)的厚度对ONO层漏电的影响.结果表明,采用较薄的底氧和较厚的顶氧,既能保证较高的临界电场强度,又能获得较薄的等效氧化层厚度,提高耦合率,降低编程电压.