Compact Two‐State‐Variable Second‐Order Memristor Model

A key requirement for using memristors in functional circuits is a predictive physical model to capture the resistive switching behavior, which shall be compact enough to be implemented using a circuit simulator. Although a number of memristor models have been developed, most of these models (i.e., first‐order memristor models) have utilized only a one‐state‐variable. However, such simplification is not adequate for accurate modeling because multiple mechanisms are involved in resistive switching. Here, a two‐state‐variable based second‐order memristor model is presented, which considers the axial drift of the charged vacancies in an applied electric field and the radial vacancy motion caused by the thermophoresis and diffusion. In particular, this model emulates the details of the intrinsic short‐term dynamics, such as decay and temporal heat summation, and therefore, it accurately predicts the resistive switching characteristics for both DC and AC input signals.     

Exploring Multifunctionality in MgO-Based Magnetic Tunnel Junctions with Coexisting Magnetoresistance and Memristive Properties

Magnetic tunnel junctions (MTJs) and memristors are two key emerging nanotechnologies that attracted significant interest for potential applications at the forefront of the digital revolution, including sensing, data storage, and non-conventional computation. The co-integration of these phenomena into a single multifunctional device is an important step toward harnessing the re-programmability of memristive systems with the high yield and varied functionality of MTJs. This study demonstrates the co-existence of magnetoresistance and memristive properties on MgO-based MTJs. These devices show a magnetoresistance with a linear response as a function of a magnetic field and no hysteresis, which are the requirements for good magnetic field sensors, as well as demonstrating a non-volatile and quasi-analogue memristive behavior as a function of an applied electrical field down to nanosecond pulses. Furthermore, by doping the oxide barrier, the memristive power consumption is lowered by 20% giving the multi-functionality of the devices a promising scalability potential. This study also shows that, memristive switching can be reversibly used to completely suppress and recover the spintronic functionalities. These results can pave the way for a seamless co-integration of memristors and spintronic devices in complex reprogrammable circuits addressing applications such as reprogrammable multifunctional field sensor arrays and neuromorphic computing.     

All-Optically Controlled Memristor for Optoelectronic Neuromorphic Computing

Neuromorphic computing (NC) is a new generation of artificial intelligence. Memristors are promising candidates for NC owing to the feasibility of their ultrahigh-density 3D integration and their ultralow energy consumption. Compared to traditional electrical memristors, the emerging optoelectronic memristors are more attractive owing to their ability to combine the advantages of both photonics and electronics. However, the inability to reversibly tune the memconductance with light has severely restricted the development of optoelectronic NC. Here, an all-optically controlled (AOC) analog memristor is realized, with memconductance that is reversibly tunable over a continuous range by varying only the wavelength of the controlling light. The device is based on the relatively mature semiconductor material InGaZnO and a memconductance tuning mechanism of light-induced electron trapping and detrapping. It is found that the light-induced multiple memconductance states are nonvolatile. Furthermore, spike-timing-dependent plasticity learning can be mimicked in this AOC memristor, indicating its potential applications in AOC spiking neural networks for highly efficient optoelectronic NC.     

Layered (C6H5CH2NH3)2CuBr4 Perovskite for Multilevel Storage Resistive Switching Memory

Although there have been attempts to use non‐lead based halide perovskite materials as insulating layers for resistive switching memory, the ratio of low resistance state (LRS) to high resistance state (HRS) ( = ON/OFF ratio) and/or endurance is reported to be mostly lower than 10³. Resistive switching memory characteristics of layered (BzA)₂CuBr₄ (BzA = C₆H₅CH₂NH₃) perovskite with high ON/OFF ratio and long endurance are reported here. The X‐ray diffraction (XRD) pattern of the deposited (BzA)₂CuBr₄ layer shows highly oriented (00l) planes perpendicular to a Pt substrate. An Ag/PMMA/(BzA)₂CuBr₄/Pt device shows bipolar switching behavior. A forming step at around +0.5 V is observed before the repeated bipolar switching at the SET voltage of +0.2 V and RESET voltage of ‐0.3 V. The ON/OFF ratio as high as =10⁸ is monitored along with an endurance of ≈2000 cycles and retention time over 1000 s. The high ON/OFF ratio enables multilevel storage characteristics as confirmed by changing the compliance currents. Ohmic conduction at the LRS and Schottky emission at HRS are involved in electrochemical metallization process. The bipolar resistive switching property is retained after storing the device at ambient condition under relative humidity of about 50% for 2 weeks, which indicates that (BzA)₂CuBr₄ is stable memory material.     

Functional Demonstration of a Memristive Arithmetic Logic Unit (MemALU) for In‐Memory Computing

The development of in‐memory computing has opened up possibilities to build next‐generation non‐von‐Neumann computing architecture. Implementation of logic functions within the memristors can significantly improve the energy efficiency and alleviate the bandwidth congestion issue. In this work, the demonstration of arithmetic logic unit functions is presented in a memristive crossbar with implemented non‐volatile Boolean logic and arithmetic computing. For logic implementation, a standard operating voltage mode is proposed for executing reconfigurable stateful IMP, destructive OR, NOR, and non‐destructive OR logic on both the word and bit lines. No additional voltages are needed beyond “V_P” and its negative component. With these basic logic functions, other Boolean functions are constructed within five devices in at most five steps. For arithmetic computing, the fundamental functions including an n‐bit full adder with high parallelism as well as efficient increment, decrement, and shift operations are demonstrated. Other arithmetic blocks, such as subtraction, multiplication, and division are further designed. This work provides solid evidence that memristors can be used as the building block for in‐memory computing, targeting various low‐power edge computing applications.     

In-Memory Computing with Memristor Content Addressable Memories for Pattern Matching

The dramatic rise of data-intensive workloads has revived application-specific computational hardware for continuing speed and power improvements, frequently achieved by limiting data movement and implementing “in-memory computation”. However, conventional complementary metal oxide semiconductor (CMOS) circuit designs can still suffer low power efficiency, motivating designs leveraging nonvolatile resistive random access memory (ReRAM), and with many studies focusing on crossbar circuit architectures. Another circuit primitive—content addressable memory (CAM)—shows great promise for mapping a diverse range of computational models for in-memory computation, with recent ReRAM–CAM designs proposed but few experimentally demonstrated. Here, programming and control of memristors across an 86 × 12 memristor ternary CAM (TCAM) array integrated with CMOS are demonstrated, and parameter tradeoffs for optimizing speed and search margin are evaluated. In addition to smaller area, this memristor TCAM results in significantly lower power due to very low programmable conductance states, motivating CAM use in a wider range of computational applications than conventional TCAMs are confined to today. Finally, the first experimental demonstration of two computational models in memristor TCAM arrays is reported: regular expression matching in a finite state machine for network security intrusion detection and definable inexact pattern matching in a Levenshtein automata for genomic sequencing.     

Adaptive Crystallite Kinetics in Homogenous Bilayer Oxide Memristor for Emulating Diverse Synaptic Plasticity

A critical routine for memristors applied to neuromorphic computing is to approximate synaptic dynamic behaviors as closely as possible. A type of homogenous bilayer memristor with a structure of W/HfO_y/HfO_x/Pt is designed and constructed in this paper. The memristor replicates the structure and oxygen vacancy (V_O) distribution of a complete synapse and its Ca²⁺ distribution, respectively, after the forming process. The detailed characterizations of its atomic structure and phase transformation in and near the conductive channel demonstrate that the crystallite kinetics are adaptively coupled with the V_O migration prompted by directional external bias. The extrusion (injection) of the V_Os and the subsequent crystallite coalescence (separation), phase transformation, and alignment (misalignment) resemble closely the Ca²⁺ flux and neurotransmitter dynamics in chemical synapses. Such adaptation and similarity allow the memristor to emulate diverse synaptic plasticity. This study supplies a kinetic process of conductive channel theory for bilayer memristors. In addition, our memristor has very low energy consumption (5–7.5 fJ per switching for a 0.5 µm diameter device, compatible with a synaptic event) and is therefore suitable for large‐scale integration used in neuromorphic networks.     

Donor‐Induced Performance Tuning of Amorphous SrTiO3 Memristive Nanodevices: Multistate Resistive Switching and Mechanical Tunability

Metal–oxide valence‐change memristive devices are the key contenders for the development of multilevel nonvolatile analog memories and neuromorphic computing architectures. Reliable low energy performance and tunability of nonlinear resistive switching dynamics are essential to streamline the high‐density circuit level integration of these devices. Here, manipulation of room temperature‐synthesized defect chemistry is employed to enhance and tune the switching characteristics of high‐performance amorphous SrTiO₃ (a‐STO) memristors. Substitutional donor (Nb) doping with low concentrations in the a‐STO oxide structure allows extensive improvements in energy requirements, stability, and controllability of the memristive performance, as well as field‐dependent multistate resistive switching. Evidence is presented that room temperature donor doping results in a modified insulator oxide where dislocation sites act as charge carrier modulators for low energy and multilevel operation. Finally, the performance of donor‐doped a‐STO‐based memristive nanodevices is showcased, with the possibility of mechanical modulation of the nonlinear memristive characteristics of these devices demonstrated. These results highlight the potential of donor‐doped a‐STO nanodevices for high‐density integration as analog memories and multifunctional alternative logic elements.     

A family of memristor‐based reactance‐less oscillators

In this paper, we present for the first time a family of memristor‐based reactance‐less oscillators (MRLOs). The proposed oscillators require no reactive components, that is, inductors or capacitors, rather, the ‘resistance storage’ property of memristor is exploited to generate the oscillation. Different types of MRLO family are presented, and for each type, closed form expressions are derived for the oscillation condition, oscillation frequency, and range of oscillation. Derived equations are further verified using transient circuit simulations. A comparison between different MRLO types is also discussed. In addition, detailed fabrication steps of a memristor device and experimental results for the first MRLO physical realization are presented. Copyright © 2013 John Wiley & Sons, Ltd.