Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.     

纳米碳酸钙制备过程中添加剂作用机理探讨

采用鼓泡碳化法 ,在最佳反应温度、反应物浓度的条件下 ,考察了添加剂对产物形状及粒径大小的影响 ,得到了直径为 2 0～ 30nm、长径比在 2 0左右且分散性能良好的针状纳米碳酸钙 ,并对添加剂作用机理进行了分析。     

PEG20000中试放大的工艺研究

在一定温度和催化剂作用下 ,分别利用本体聚合和溶剂聚合的方法 ,在 1L、10 0L不锈钢高压反应釜中合成了相对分子质量为 2 0 0 0 0的聚乙二醇 ,并讨论了聚合反应机理 ,研究了催化剂用量、反应温度、反应时间对聚合反应的影响。经过红外、核磁共振、凝胶色谱、化学分析等方法对产物进行了表征。     

硼酸铝晶须增强环氧树脂和双马来酰亚胺树脂体系的研究

本文以硼酸铝晶须为增强剂，以4，5-环氧环己烷-1，2-二甲酸二缩水甘油酯(TDE-85)，甲基纳狄克酸酐(MNA)、N，N’-二胺基二苯甲烷型双马来酰亚胺(BMI)/O，O′-二烯丙基双酚A(BA)体系分别作为基体制备晶须增强复合材料。研究了晶须对树脂的尺寸、表面处理方法、含量对树脂体系力学性能和热性能的影响；通过扫描电子显微镜(SEM)分析了浇注体的弯曲、冲击断口，研究晶须的增强机理。     

石油工程项目管理机制

为了妥善处理石油工程项目中的委托-代理关系,研究了委托-代理模型和石油工程项目管理中的激励约束机制,分析了激励机制、监督机制和选择机制在石油工程项目运行管理中的重要性.只有用有效的契约去激励技术服务公司,才能使服务公司在追求自身效益最大化的同时也为实现石油公司的最大效益而尽最大努力;只有对技术服务公司的作业实施监督,才能形成对技术服务公司的有效约束;采用激励性承包方式、实施综合性评标和组建工程项目动态联盟能够防止逆向选择.分析表明,在最优激励安排下,激励强度与项目面临的不确定性、承包商的边际成本及其风险规避系数负相关,与承包商的边际生产率正相关,还与其他可观测变量相关.在最优监督水平下,作业公司的边际生产率越高,边际成本越低,越容易监督,监督带来的边际收益越高.对于那些监督比较困难的项目,可以通过加强惩罚力度的方式弥补难以有效监督的不足.激励性承包方式可以减小逆向选择造成的危害,组建动态联盟可以进一步加强激励作用,降低道德风险,解决逆向选择问题.参8     

Corrosion Inhibition Mechanism with Spilt Cell Technique of Rare Earth Metal on LC4 Al Alloy

A new method of studying the corrosion inhibition mechanism of rare earth metal(REM) on LC4 Al alloy with the spilt cell technique was studied. The principle and experimental method of the spilt cell technique were analyzed. By measuring the change of net-electric current between the two electrodes caused by the change of the amount of oxygen in the solution and the addition of CeCl₃, the influence of corrosive performance of CeCl₃ on LC4 super-power aluminum alloy in the 0.1 mol·L⁻¹ NaCl solution was investigated. Meanwhile, the conditional changes of pH values, CeCl₃ solution, additire and time of performance were also studied. Finally, the features of electrode surface were revealed by using SEM and X-ray energy-dispersive spectrometry (EDS). By combining these with other electric chemical techniques, such as potential-time curve, polarization curve et al.     

真空制盐蒸发结晶器的设计与实践

真空蒸发制盐外热式强制逆循环轴向出料蒸发结晶器，经多个厂家生产应用实践证明是成功的，具有生命力的。这种新型结构，作为一项新技术新设备应加强研究，总结提高，推广应用。不断完善。文章从流体力学、结晶机理角度要求，到具体工程设计参数和材质选用。论述了该罐的特点。     

Parallel path consistency

Filtering algorithms are well accepted as a means of speeding up the solution of the consistent labeling problem (CLP). Despite the fact that path consistency does a better job of filtering than arc consistency, AC is still the preferred technique because it has a much lower time complexity. We are implementing parallel path consistency algorithms on multiprocessors and comparing their performance to the best sequential and parallel arc consistency algorithms.^(1,2) (See also work by Kerethoet al. ⁽³⁾ and Kasif⁽⁴⁾) Preliminary work has shown linear performance increases for parallelized path consistency and also shown that in many cases performance is significantly better than the theoretical worst case. These two results lead us to believe that parallel path consistency may be a superior filtering technique. Finally, we have implemented path consistency as an outer product computation and have obtained good results (e.g., linear speedup on a 64K-node Connection Machine 2).     

A VLSI architecture for a half-edge-based corner detector

Corner detection is a low-level feature detection operator that is of great use in image processing applications, for example, optical flow and structure from motion by image correspondence. The detection of corners is a computationally intensive operation. Past implementations of corner detection techniques have been restricted to software. In this paper we propose an efficient very large-scale integration (VLSI) architecture for detection of corners in images. The corner detection technique is based on the half-edge concept and the first directional derivative of Gaussian. Apart from the location of the corner points, the algorithm also computes the corner orientation and the corner angle and outputs the edge map of the image. The symmetrical properties of the masks are utilized to reduce the number of convolutions effectively, from eight to two. Therefore, the number of multiplications required per pixel is reduced from 1800 to 392. Thus, the proposed architecture yields a speed-up factor of 4.6 over conventional convolution architectures. The architecture uses the principles of pipelining and parallelism and can be implemented in VLSI.