新型图形化 SOI LDMOS结构的性能分析

提出一种图形化SOILDMOSFET结构,埋氧层在器件沟道下方是断开的,只存在于源区和漏区.数值模拟结果表明,相对于无体连接的SOI器件,此结构的关态和开态击穿电压可分别提高57%和70%,跨导平滑,开态I-V曲线没有翘曲现象,器件温度低100K左右,同时此结构还具有低的泄漏电流和输出电容.沟道下方开硅窗口可明显抑制SOI器件的浮体效应和自加热效应.此结构具有提高SOI功率器件性能和稳定性的开发潜力.     

多晶硅薄膜晶体管自加热效应温度分布的有限元模拟

采用有限元方法模拟了n型MILC低温多晶硅薄膜晶体管在直流自加热应力下器件的温度分布．通过对器件沟道温度分布的稳态及瞬态模拟,研究了器件功率密度、衬底材料类型和器件宽长等关键因素的影响．确认了改善器件自加热退化的有效途径,同时有助于揭示多晶硅薄膜晶体管自加热退化的内在机制．     

Dynamic surface temperature measurements in SiC epitaxial power diodes performed under single-pulse self-heating conditions

Semiconductor devices development, design and optimization require the use of computer simulation tools able to predict the entire device safe operating area (SOA), something that it is not always possible due to limitations in some of the physical models in predicting certain properties of device operation under extreme conditions (i.e. high carrier injection levels and high temperature). In order to improve our understanding of device operation under these extreme conditions experimental data of the dynamic IV characteristics and temperature time evolution and space distribution are required. The experimental data obtained are then used in the development of improved physical models and simulation tools.

In this work, dynamic surface temperature measurements as a function of current pulse peak density and length were performed on SiC-PiN epitaxial power diodes. The measurements were carried out using an infrared (IR) microscope developed in our lab capable of measuring space and time surface temperature distributions in semiconductor devices operating under self-heating conditions [Solid State Electron 2001;45(12):2057]. The minimum detected spot size is 15 μm, while the signal raising time is detector limited to about 1 μs. The lowest detectable temperature increment is at least 10 °C over room temperature.

Using this instrument, dynamic thermal phenomena in 4.5 kV SiC-PiN epitaxial power diodes [Mater Sci Forum 2001;353–356:727] subjected to 1 ms long 100–6000 A/cm² and 0.1–5 ms long 3000 A/cm² current pulses have been studied. The possibility of obtaining dynamic surface temperature information from SiC electronic devices operating under self-heating conditions with time constants in the order of ms is demonstrated.     

自热食品加热过程中的食用安全性研究

目的 基于消费者对于自热食品目前存在的担忧,探究自热包在自加热过程中由于挥发性气体、塑化剂迁移等带来的安全性问题。方法 选取6个品牌的市售自加热包,测定其发热过程中生成气体种类、排放量及在食物中残留情况,通过对比相应限值,对其危害性进行分析。结果 6种常见市售自加热包在发热过程中共检出17种有害气体,释放量均低于大气污染及吸入毒性的规定限值。但自加热过程会使食物中混入三氯甲烷,且橄榄油中的三氯甲烷残留多于米饭中的。随加热时间延长,三氯甲烷残留量呈现先升高后下降的趋势,最终残留量接近规定限值。食品自加热后未发现塑化剂残留。结论 自热食品加热过程中潜在的主要安全隐患为包装袋的三氯甲烷残留,应避免自热过程中产生的气体与食品直接接触。本研究为自热食品自加热过程中危害分析以及后续自热食品及其包装的研发提供了数据支撑。     

棉花的热危险性及其影响因素的研究

为评估棉花的热危险性,采用自热和自燃点测试装置,研究了含水量、含油量、堆积密度等对棉花自热性能的影响规律,以及立方体金属网篮的不同体积对棉花自燃温度的影响。结果表明:含水量、含油量及堆积密度越高,棉花内部温度越高,热危险性越大。但水的质量分数在0~50%的范围内,脱脂棉和长绒棉两种棉花均不属于自热物质;当油的质量分数为5%和10%时,长绒棉发生自燃时最高温度分别为635.6 ℃和539.7 ℃,属于自热物质;当油的质量分数为5%、10%和15%时,脱脂棉最高温度分别上升至161.7、169.8 ℃和184.1 ℃。立方体金属网篮的体积越大,棉花的自燃温度越低;研究发现,立方体网篮体积的对数（logV）和自燃温度的倒数（1/T）成线性关系,根据拟合曲线可预测不同体积下棉花的自燃温度。     

低周疲劳损伤过程的自热温升变化特征

通过对低周疲劳过程中试样的自热温升红外测试,讨论了不同控制应变下,试样的温升变化规律及其表面的温度分布与循环数、控制应变水平及加载频率的关系。探讨了循环疲劳损伤与温升变化的对应关系及其能量变化规律。     

自发电采暖鞋的设计

介绍了电磁感应发电式自发电采暖鞋的设计,以克服当前采暖鞋存在的使用不便、使用寿命短及不够环保等问题;根据行走中人体工程学的分析和计算,证明采用线圈-永磁铁芯的发电方式,人体行走能提供的发电功率为每只脚6.6W,可以满足鞋内的取暖。并做到无易损件、无污染、使用方便和经济实惠。     

硫化矿尘层氧化自热初始温度试验研究

为研究硫化矿尘氧化自热的影响因素,以硫化矿尘层氧化自热温度和产生二氧化硫时的内部温度为指标,以硫化矿尘的含硫量、矿尘层厚度和矿尘粒径为自变量,进行3因素3水平正交试验获得硫化矿尘层开始氧化自热时的初始温度和产生二氧化硫时的内部温度,利用灰色系统理论分别计算影响因素对单目标函数的关联系数和多目标函数的关联度,将多目标转换为以关联度为目标的单目标进一步计算各影响因素的平均关联度,从而得出硫化矿尘最易发生氧化自热的条件,为高硫矿山安全生产提供依据。     

基于GRNN模型的硫化矿石堆氧化自热温度预测

为得到硫化矿石堆氧化自热温度的变化规律,自主设计硫化矿石堆氧化自热模拟试验装置,以含硫量、矿石块度、升温梯度作为试验影响因素,将硫化矿石堆氧化自热温升速率作为试验判定指标,采用L9(34)正交表构造三因素三水平回归正交试验。运用MATLAB建立硫化矿石堆氧化自热温度的GRNN神经网络模型,通过K-折交叉验证优选得到GRNN神经网络的最佳光滑因子σe,并与RBF神经网络模型、灰色神经网络模型预测效果进行对比。结果表明：GRNN神经网络在小样本预测模型中网络逼近能力、收敛速度、算法稳定性等方面具有优势,对硫化矿石堆氧化自热温度的预测精度高,预测误差为3.51%。     

Temperature-Aware Electromigration Analysis with Current-Tracking in Power Grid Networks

Electromigration (EM) is a severe reliability issue in power grid networks.The via array possesses special EM characteristics and suffers from Joule heating and current crowding,closely related to EM violations.In this study,a power grid EM analysis method was developed to solve temperature variation effects for the via array EM.The new method is based on the temperature-aware EM model,which considers the effects of self-heating and thermal coupling of interconnected lines in a power grid.According to the model,the proposed methodology introduces a locality-driven strategy and current tracking to perform full-chip EM assessment for multilayered power grids.The results show that temperature due to Joule heating indeed has significant impacts on the via EM failure.The results further demonstrate that the proposed method might reasonably improve efficiency while ensuring the accuracy of the analysis.