Solid-state D102 dye sensitized/poly(3-hexylthiophene) hybrid solar cells on flexible Ti substrate

Flexible solid-state dye sensitized solar cell is an important milestone for low-cost, large scale fabrication of dye-sensitized solar cells. Flexible solid-state dye-sensitized solar cell is fabricated for the first time on titanium substrates using D102 sensitizer and a sputtered platinum semi-transparent cathode. Devices are illuminated from the cathode side since titanium substrates are non-transparent. Due to rear-side illumination, significant proportion of radiation is absorbed and scattered by poly(3-hexylthiophene) and platinum, respectively. Limiting the amount of platinum and poly(3-hexylthiophene), up to a point, is found to enhance device efficiency. The amount of platinum and poly(3-hexylthiophene) is optimized on glass substrates before fabrication of flexible devices on titanium substrates. The rough surface of titanium substrates is smoothened until a mirror finish and the growth of a thin layer of native oxide enhanced the device efficiency. Under optimized conditions, an efficiency of 1.20% is obtained for devices fabricated on titanium foil substrates. The lower efficiency as compared to conventional devices is mainly due to light absorption/scattering from the poly(3-hexylthiophene) and platinum layers.     

Design and fabrication of a planar patch-clamp substrate using a silicon-on-insulator wafer

noise.     

An improved analytical model of 4H-SiC MESFET incorporating bulk and interface trapping effects

An improved analytical model for the current-voltage (I-V) characteristics of the 4H-SiC metal semiconductor field effect transistor (MESFET) on a high purity semi-insulating (HPSI) substrate with trapping and thermal effects is presented. The 4H-SiC MESFET structure includes a stack of HPSI substrates and a uniformly doped channel layer. The trapping effects include both the effect of multiple deep-level traps in the substrate and surface traps between the gate to source/drain. The self-heating effects are also incorporated to obtain the accurate and realistic nature of the analytical model. The importance of the proposed model is emphasised through the inclusion of the recent and exact nature of the traps in the 4H-SiC HPSI substrate responsible for substrate compensation. The analytical model is used to exhibit DC I-V characteristics of the device with and without trapping and thermal effects. From the results, the current degradation is observed due to the surface and substrate trapping effects and the negative conductance introduced by the self-heating effect at a high drain voltage. The calculated results are compared with reported experimental and two-dimensional simulations (Silvaco^®-TCAD). The proposed model also illustrates the effectiveness of the gate-source distance scaling effect compared to the gate-drain scaling effect in optimizing 4H-SiC MESFET performance. Results demonstrate that the proposed I-V model of 4H-SiC MESFET is suitable for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.     

大功率LED散热用微通道铝基板的有限元仿真

对带微通道的铝基板上封装的不同功率LED,用Comsol Multiphysics软件对其温度场进行了有限元模拟,重点研究了微通道的孔大小、孔间距、绝缘层的厚度和热导率对基板散热性能的影响,结果表明:铝基板厚度为1.5mm左右,微通道方形孔,孔长0.8mm,孔间距0.8mm,绝缘层厚度50μm,热导率1.5 W/(m·K),为最佳散热性能铝基板.微通道铝基板封装3W灯珠与普通铝基板和氮化铝基板相比,热阻分别下降了5.44和3.21℃/W,表明微通道铝基板能更好地满足大功率LED散热的需求.     

玻璃衬底上制备GaN薄膜的研究进展

近年来,GaN基发光二极管(LED)的发展异常迅速,以玻璃为衬底的LED具有成本低、可大面积化生产等优点而引起了国内外许多科研机构的广泛研究兴趣.但由于普通玻璃较低的软化温度(500～ 600℃)以及与GaN之间存在较大的晶格失配问题,一直阻碍其发展.重点综述了玻璃衬底上生长GaN薄膜的方法以及改善外延层晶体质量的技术.分别介绍了两种在普通玻璃上生长GaN的方法,即低温生长和局部加热生长,同时详述了采用缓冲层和横向外延过生长(ELO)技术对外延GaN晶体质量的影响.对局部加热、ELO等技术在玻璃衬底LED方面的应用进行了分析和预测,认为以玻璃为衬底的LED终会取得快速地发展.     

图案化GaAs衬底外延InP局域表面成核层生长

使用光学显微镜、原子力显微镜和微区喇曼光谱对在纳球光刻图案化GaAs衬底的孔洞区进行金属有机化学气相沉积(MOCVD)进而对InP成核层进行了研究.实验结果表明,该局域表面InP的成核层生长和孔洞的大小、方向、位置关系不大,与MOCVD的生长条件相关.与渐变缓冲层生长相比,在InP的成核层中没有出现穿透位错,其结晶质量随着温度的升高而提高,但其表面粗糙度会随着温度的升高而增加,这个现象可能和它的3D岛状生长有关.AFM测试结果表明,提高Ⅴ/Ⅲ比可以在较低的温度下抑制其表面粗糙度降至纳米量级.微区喇曼光谱测试表明,在适当条件生长下可获得InP成核层的二维生长方式.该研究为进一步基于ART机理在二维图案化GaAs衬底开展InP异质外延研究奠定基础.     

数模混合高速集成电路封装基板协同设计与验证

介绍了数模混合高速集成电路(IC)封装的特性以及该类封装协同设计的一般分析方法.合理有效的基板设计是实现可靠封装的重要保障,基于物理互连设计与电设计协同开展的思路,采用Cadence APD工具以及三维电磁场仿真工具实现了特定数模混合高速集成电路(一款探测器读出电路)的封装设计与仿真论证,芯片封装后组装测试,探测器系统性能良好,封装设计达到预期目标.封装电仿真主要包含:封装信号传输通道S参数提取、电源/地网络评估,探测器读出芯片封装体互连通道设计能满足信号带宽为350 MHz(或者信号上升时间大于1 ns)的高速信号的传输.封装基板布线设计与基板电设计协同分析是提高数模混合高速集成电路封装设计效率的有效途径.     

Fabrication and characterization of low-cost ultrathin flexible polyimide interposer

A passive interposer, which is a way to bridge the feature gap between the integrated circuit (IC) and the package substrate, is a key building block for high performance 3-D systems. In this paper, polyimide (PI) is proposed as an alternative to glass and silicon based interposers for cost-effective 2.5-D/3-D IC integration. The development of interconnect technology using an ultrathin flexible polyimide interposer (UFPI) for 2.5-D/3-D packaging applications is described in detail. A semi-additive process consisting of copper seed layer deposition, photolithography, and electrolytic copper pattern plating is used for fabricating a double-sided flexible fan out interposer. A UFPI with electrodeposited micro-scale copper (Cu) fine patterns and laser drilling microvia is investigated using a scanning electron microscope (SEM), energy-dispersive spectrometry (EDS), X-ray spectrometry, and an optical 3-D profilometer. The UFPI with fine pitch on 12.5 μm thin PI substrates has been demonstrated. The result is a proof-of-concept to exploit the opportunities of cost-effective 2.5D flexible interposer production.     

TEM原位光电双功能样品杆改造及电源系统优化设计

为了研制用于透射电子显微镜(TEM)的光学和电学双功能原位测试样品杆,在理解国外进口电学原位样品杆电路和电极结构的基础上,引入微型LED芯片作为发光源对其进行光电双功能升级改造,并通过优化光电双功能基片供电电源系统以保障TEM清晰成像。测试结果表明,利用自制的基片供电电源,改造后的电学测试样品杆能同时测试样品的光学和电学特性,且透射电子显微镜成像清晰稳定。