An efficient reversible data hiding scheme using prediction and optimal side information selection

In this paper, we present an efficient histogram shifting (HS) based reversible data hiding scheme for copyright protection of multimedia. Firstly, an improved HS based multi-layer embedding process for rhombus prediction is employed by introducing a control parameter to explore the correlation of prediction errors. A rate-distortion model for HS embedding is then developed for optimal side information selection, which is especially suitable for low payload reversible data hiding when only a single layer embedding is required. Finally, a modified location map is constructed to facilitate the compression of location map and further increase the embedding capacity. Compared with similar schemes, experimental results demonstrate the superior performance of the proposed scheme in the terms of embedding capacity and stego-image quality.     

基于MAC序列的相位编码准连续波的研究与应用

本文在讨论用二相编码信号构成的准连续波的数学模型和模糊函数的基础上,引入新的二元序列--MAC序列,并对其产生以及自相关特性进行了详细研究。通过对采用该序列编码的准连续波信号的周期单码重复时和多码重复的模糊函数进行仿真,其结果具有很好的图钉状,即有较高的距离和多普勒分辨率;并将MAC序列的相位编码准连续波应用在波形设计中,脉压仿真结果表明相比较m序列码,MAC序列更适用于目标检测。     

355 nm脉冲激光诱导等离子体开关削波

利用激光诱导等离子体开关技术,对355 nm脉冲激光自削波进行了实验和理论研究。分别采用5种不同焦距的透镜,集中讨论了透镜焦距及激光器输出单脉冲能量对脉宽压缩的影响,发现采用焦距为200 mm的透镜能够获得最佳的脉冲压缩效果。在聚焦透镜焦距200 mm,单脉冲能量160 mJ时,获得最短脉宽3.47 ns;在激光电离Cu小孔内壁表面及空气击穿共同作用下,获得了脉宽最短达2.11 ns的脉冲激光输出。此外,根据实验结果得到了355 nm激光空气击穿阈值,并与理论估算值进行比较,两者结果较为一致。     

基于梯度的CCSDS压缩码流控制算法研究

为了优化CCSDS压缩标准的率失真特性,提出了一种基于梯度的CCSDS压缩码流控制算法。该算法采用梯度模值来描述图像各编码段的纹理复杂度,进而用模值之和表示各段所包含的信息量。首先计算出各编码段梯度模值之和,并将其相加得到整幅图像的梯度模值之和,根据前者在后者中所占比例,将码流容量分配给各编码段。采用MATLAB对新算法、CCSDS标准算法及Jin算法进行仿真测试,比较三者图像的恢复质量。同时,测试新算法和Jin算法分配码流所需时间,并进行对比。实验结果表明,在图像恢复质量方面,新算法优于CCSDS标准算法,稍逊于Jin算法,但是新算法的实时性比Jin算法好。因此,基于梯度的码流控制算法可应用于CCSDS标准中。     

极大规模集成电路测试技术发展

集成电路作为新一代信息战略产业的基础,工艺、封装、应用的发展对测试提出了诸多挑战,同时测试作为集成电路产业链的一环,与设计、制造、封装等环节紧密相联。阐述了集成电路设计中高速、高集成度及测试成本对测试的挑战以及相应的测试解决方案,同时对测试与设计、封装、应用等产业链环节联接的典型技术如测试仿真到测试向量转换、inkless map、测试自动化数据等进行了描述。     

基于FPGA+DSP架构视频处理系统设计

实时图像处理技术在工业、医学、军事和商业等领域有广泛的应用。基于FPGA+DSP架构的视频处理系统充分发挥了各自器件的长处,不仅设计周期短,开发费用低,而且设计灵活,更改方便,功耗较低,便于实现系统的小型化。因此对基与FPGA+DSP架构的视频处理系统进行研究和设计具有重要的意义[1]。     

基于LOCO—I算法的星载图像无损压缩的FPGA实现

LOC0-I图像无损压缩算法是JPEG--LS标准的核心算法．文中针对于星载图像无损压缩的具体应用,充分利用了流水和并行技术,给出了基于该算法的高速星载图像无损压缩核的设计和实现．压缩验证系统实验结果表明,该设计可每周期处理一个像素,50MHz频率下数据处理速度可达400Mbps,满足星载图像无损压缩的实际要求．     

基于图像平滑度的WBCT算法研究与改进

由于WBCT压缩算法对于不同平滑度图像无差别滤波,使得对于较平滑的图像,其恢复图像效果要低于一般小波编码方法,为此,本文针对不同平滑度的图像,通过定义图像平滑度,对图像进行分类,利用多方向多尺度临界采样,进行不同程度的方向滤波。笔者利用变换后的小波系数的特点,采用SPIHT算法实现嵌入式编码,从而改进了WBCT压缩算法...     

An Efficient Architecture for a Lifted 2D Biorthogonal DWT

This paper presents a new algorithm for a 2D non-separable lifted bi-orthogonal wavelet transform. The algorithm is derived by factoring complementary pairs of wavelet transform 2D filters. The results are efficient architectures for real time signal processing, which do not require transpose memory for the 2D processing of data. The proposed architecture exploits in place implementation, inherit from the algorithm, and can take advantage of both vertical and horizontal parallelism in the direct implementation. The processing in our architecture is scheduled by carefully pipelining the lifted steps, which allows for up to four times faster processing than the direct implementation. The proposed architecture operates at high speed, consumes low power and has reduced computational complexity as compared to previously published filter and lifted based bi-orthogonal wavelet architectures.M. Alam (Student) is currently M.Sc. student in the Department of Electrical and Computer Engineering at University of Calgary. His research interest includes VLSI signal processing. He is recipient of iCORE International Graduate Scholarship.Wael Badawy (Ph.D. 00, M.Sc 98, 97; B.Sc. 94) is an associate professor in the Department of Electrical and Computer Engineering. He holds an adjunct professor in the Department of Mechanical Engineering, University of Alberta.Dr. Badawys research interests are in the areas of: Microelectronics, VLSI architectures for video applications with low-bit rate applications, digital video processing, low power design methodologies, and VLSI prototyping. His research involves designing new models, techniques, algorithms, architectures and low power prototype for novel system and consumer products. Dr. Badawy authored and co-authored more than 100 peer reviewed Journal and Conference papers and about 30 technical reports. He is the Guest Editor for the special issue on System on Chip for Real-Time Applications in the Canadian Journal on Electrical and Computer Engineering, the Technical Chair for the 2002 International Workshop on SoC for real-time applications, and a technical reviewer in several IEEE journals and conferences. He is currently a member of the IEEE-CAS Technical Committee on Communication. Dr. Badawy was honored with the 2002 Petro Canada Young Innovator Award, 2001 Micralyne Microsystems Design Award and the 1998 Upsilon Pi Epsilon Honor Society and IEEE Computer Society Award for Academic Excellence in Computer Disciplines. He is currently the Chairman of the Canadian Advisor Committee (CAC) and Head of the Canadian Delegation on ISO/IEC/JTC1/SC6 Telecommunications and Information Exchange Between Systems. Member, The Canadian Advisory Committee for the Standards Council of Canada-Subcommittee 29: Coding of Audio, Picture Multimedia and Hypermedia Information, and Canadian Delegate, The ISO/IEC MPEG standard committee. He is a voting Member on the VSI Alliance. He is also the Chair of the IEEE-Southern Alberta Society-Computer Chapter.Vassil S. Dimitrov was born in Plovdiv, Bulgaria, in 1964. He received his Ph.D. degree in mathematics in 1995 from the Mathematical Institute of the Bulgarian Academy of Sciences. Since then, he has spent two years as a postdocral fellow at the VLSI Research Group, University of Windsor, Canada, one year as a research scientist at the Reliable Software Technology Corporation, Virginia, USA, one year as a chief research scientist at the Signal Processing and Computer Technology Laboratory, Helsinki University of Technology, Finland, and one year as an Associate Professor at the University of Windsor, Canada. Since July 2001 he has held the position of Associate Professor at the Department of Electrical and Computer Engineering, University of Calgary, Canada. His main interests are in the area of number theoretic algorithms, computational complexity, cryptography, optimization theory, fast algorithms for digital signal processing and related topics. Dr. Dimitrov is a member of the New York Academy of Sciences.Graham Jullien (Fellow IEEE) was educated in the United Kingdom, receiving degrees, in Electrical Engineering, from the Universities of Loughborough, Birmingham and Aston (Ph.D., 1969). He was a student engineer and data processing engineer at English Electric Computers, UK, from 1961 to 1966, and a visiting senior research engineer at the Central Research Laboratories of EMI Ltd., UK, from 1975 to 1976. From 1969 until 2000 he was with the Department of Electrical and Computer Engineering at the University of Windsor, Ontario, Canada, where he held the rank of University Professor and was the Director of the VLSI Research Group. Since January 2001, he has been with the Department of Electrical and Computer Engineering at the University of Calgary, where he holds the iCORE Research Chair in Advanced Technology Information Processing Systems. He is a member of the Board of Directors of the Canadian Microelectronics Corporation (CMC) and is a member of the Steering Committee and Board of Directors of the Micronet Network of Centres of Excellence. He has published widely in the fields of Digital Signal Processing, Computer Arithmetic, Neural Networks and VLSI Systems, and teaches courses in related areas. He has served on the technical committees of many international conferences; he currently serves on the Editorial Board of the Journal of VLSI Signal Processing; and is a past Associate Editor of the IEEE Transactions on Computers. He hosted and was program co-chair of the 11th IEEE Symposium on Computer Arithmetic, was program chair for the 8th Great Lakes Symposium on VLSI, and was the technical program chair for the 1999 Asilomar Conference on Signals, Systems and Computers. He is general chair for the 2003 Asilomar Conference and general co-chair of the International Workshop on System-on-Chip for Real-Time Systems, Calgary, Alberta 2003.     

接收机有限带宽对多相码数字脉压的影响

限制接收机带宽是雷达系统中提高信噪比(SNR)的常用方法,相应的也会引起输出波形的失真。本文主要分析了多相码数字脉压雷达系统中,接收机有限带宽对脉压输出结果所造成的影响。运用五点滑动窗平均法在计算机上进行了模拟,并给出了仿真结果。