未来PCB市场的新变化

文章以世界IC市场发展前景为“参照物”,研究、讨论PCB未来市场发展的趋势,以及重点阐述了未来PCB新的巨大市场——数字家电产品的形成问题。     

电镀铜粒影响因素探究

随着客户需求的不断变化和对PCB产品外观越来越高的要求,我公司客户对产品外观的要求更为严格,使得我们迫切需要对于过程中影响PCB板件外观的主要因素进行控制。本文主要从电镀铜粒着手,简述铜粒产生的影响因素,并提出可行性建议,给整个铜粒状况改善提供思路和方向。     

一种用于导电油墨的特种铜粉制备研究

特种导电油墨是全印制电路技术开发与应用的关键之一。本文报道了利用硫酸铜、碳酸钠、抗坏血酸等为原料,通过固相反应获得纳米非球形铜粉方法。通过SEM、EDS分析表明,获得的产物为一种柱状的高纯铜粉,直径大约500nm,可以作为全印制电路技术用高性能特种油墨的开发。     

行波管电镀铜螺旋线高温处理后变色问题的实验分析

对行波管螺旋线电镀铜工艺进行了描述和分析,从实验上阐明了烧氢后螺旋线表面颜色变化的原因。实验分析表明,Ni-Cu合金化反应是导致颜色变化的主要原因,而合金化的结果使表面电导率、热导率大大降低,因此,电镀铜工艺不适合于行波管螺旋线的表面处理。在此基础上,对螺旋线镀铜工艺的其他技术方案进行了评述。     

Overview of Cu contamination during integration in a dual damascene architecture for sub-quarter micron technology

A detailed study of copper contaminating steps performed during integration of multilevel Cu metallisation in dual damascene architecture has been performed. Contamination at the wafer back and the bevel edge should make it difficult to use the same equipment for conventional technology and new copper based technology. Several barrier materials have been claimed as efficient against copper diffusion. However, during process integration, contamination issues will be faced before deposition of the barrier layers. Heavy contamination can occur either during Cu chemical mechanical polishing (CMP) or during dielectric etching and via opening on top of contacted copper lines. These residues, concentrated at the dielectric surface, could result in current leakage and shorts between interconnection lines. Several cleaning solutions to remove metal contamination are reviewed and their efficiencies are compared.     

导通孔电镀铜填充技术

概述了下一代PCB用镀铜层导通孔填充技术。     

Achievement of high planarization efficiency in CMP of copper at a reduced down pressure

We report improved planarization efficiency (ratio of step height reduction and removed layer thickness) in chemical-mechanical planarization (CMP) of copper lines at a down pressure of 2 psi. The CMP slurry used to achieve these results contains fumed silica particles (abrasive), β-alanine (surface complexing agent) and H₂O₂ (oxidizer), combined with dissolution inhibiting ammonium dodecyl sulfate (ADS) and/or low concentrations (≤1 mM) of benzotriazole (BTAH) at a solution pH of 4.0. When only ADS or BTAH is used, Cu dissolution rate is reduced, but at the cost of somewhat low planarization efficiency. Combination of ADS (typically 3 mM) and BTAH (≤1 mM) in the slurry significantly improves both the surface polish rates and the planarization efficiency. The processed surface (examined by optical profilometry) is noticeably defect-free for this particular system. The mechanisms of surface dissolution and passivation are discussed, and contact angle data are used to elucidate the surface passivating nature of the inhibitor films. The results presented here are relevant for further developments in the area of low pressure CMP of Cu lines overlying fragile low-k dielectrics in the new interconnect structures.     

铜布线化学机械抛光的失效研究

分析了铜电连接在今后晶片制造中的主导作用,阐述了铜布线的结构,即在由钽作为阻挡层及采用电镀铜形成的电连接的情况下,抛光规律符合经典普莱斯顿方程;在粗抛磨料采用氧化铝,精抛配比采用武亚红提出的方案情况下,采用旋转式低速较大下压力情况下抛光,整个晶片依然存在较大的不均匀性。分析100μm线宽的碟形缺陷会逐渐减小但最后会有少许增大。整个晶片的侵蚀会和其图案密度成正比,但在同种分布情况下,精抛时间越长,则侵蚀缺陷越大。最后指出了今后发展的高速底压力会显著解决当前不均匀性问题,但失效机制分析意义依然很重大。     

Electrochemical aspects of new materials and technologies in microelectronics

Major scaling issues, which need to be addressed to continue scaling according to Moore’s law, include increase of transistor leakage due to use of thin gate oxide (about 1 nm limit for SiO₂), power (reaching 100 W/cm²) and RC delay (dielectric constant limit is 1 for air and Cu resistivity increases with scaling down the feature sizes). Integration of new materials and technologies will allow us to continue scaling and improve device performance. Examples of new materials include high-k dielectrics and strained silicon in the frond end of wafer processing, low-k carbon-doped oxide and electroplated copper in the back end of wafer processing as well as electroplated bumps, high thermal conductivity interface, heat sink and heat spreader materials in packaging. Electrochemical technologies will play an increasingly important role in silicon technology due to low cost, use of self-assembly processing and self-aligned growth ability. New electrochemical technologies in silicon processing include copper electroplating (replaced Al interconnect to reduce RC delay and increase reliability), bump electroplating (replaced wire bonding to allow increased I/O and improve reliability), and porous silicon for silicon on isolator fabrication (to reduce transistor leakage). Copper electroplating allows a low R, an excellent gap fill capability and superior materials properties with (111) textured Cu films and large grain size, and a stable and controlled process.     

用于130nm/90nm新工艺开发的铜CMP阻挡层磨料系统(英文)

通过与实验室的CMP和集成工程师合作,采用测试系统观察两种或两种以上混合配方磨料的选择比。实验数据表明,通过改变单个化学试剂组分的浓度改变磨料的选择比效果突出,磨料配方师可以简便地修改磨料配方。这种方法的优点是,如果改变集成方法或特殊膜层,可以很快地重新优化磨料。如SiN膜取代TEOW淀积氧化物膜,对新系统可以容易地重新优化磨料。介绍了几种磨料组分浓度的去除速率和选择比。