浅析220 kV线路跳闸故障及应对措施

随着经济的发展,城市配电网络以及山区高压电缆架设工程进展迅速。但是由于部分地区的自然灾害、人为事故频繁等原因,电力线路经常出现故障。比如雷电活动导致的跳闸现象。对此,本文作者通过对220kV某线雷击跳闸故障进行实例分析,寻找跳闸事故的原因。并结合多年工作经验对事故之后的改进措施提出了自己的看法。     

Impact of power electronics packaging on the reliability of grid connected photovoltaic converters for outdoor applications

This paper deals with thermal and reliability aspects of converters for grid connected photovoltaic applications (rate power approximately 100 W) which can be integrated into solar modules. The use of these Module Integrated Converters (MIC) promises a reduction of costs due to mass production. It improves behaviour of the whole photovoltaic system, as there is no voltage mismatch caused by shading effects. The electronic components of the MIC are exposed to extreme environmental conditions. Lifetime limiting factors are described. Methods to increase the lifetime of the most crucial components in the MIC, electrolytic capacitors, are described. The presented 1st generation Low Profile MIC with “optimised design” is capable of running in very high ambient temperatures. This design maximises availability of the photovoltaic system, which consequently leads to a cost reduction of the electrical energy delivered to the grid. Different realisations of how to integrate the designed Low Profile MIC into the solar module are discussed. A detailed thermal simulation is used to optimise the MIC design according to temperature and reliability issues. The models used for thermal simulation are described.     

浅谈MOSFET产品失效分析及改善措施

阐述了MOSFET产品的应用前景,说明了其封装工艺流程及注意事项,通过对MOSFET电路常见失效现象的分析验证,探讨MOSFET产品的失效机理及其影响,对相应的失效现象制定合理的失效分析方案,确保有效查找失效的具体原因,并对失效原因从设计、工艺和材料选用等方面提出改善措施。     

Signal noise perturbation on automotive mixed-mode semiconductor device generated by graded substrate defect

The semiconductor technologies evolution allows greatly reducing noise impact on products and many structures have been created to reduce its effect. However, this paper presents the apparition of a noise issue during the production of a mixed-mode device dedicated to automotive applications. The research investigations concerned the fact that failure was not detected at test level but at customer level; therefore, it was determinant to understand the root cause of this failure mode to drive corrective actions in order to secure customer. The challenge was to analyse noise in Failure Analysis (FA) without fault spatial localization results. Indeed, Light Emission Microscopy (EMMI) and Thermal Laser Stimulation (ex: Soft Defect Localization – SDL) were unable to provide any defective area in the product. The lack of failing device identification led us to combine electrical and design analyses in order to define hypothesis on the failure origin. It was then possible to drive physical investigations through different approaches, using physical cross-section, Secondary Ion Mass Spectrometry (SIMS) and Scanning Capacitance Microscopy (SCM) techniques. Finally, the obtained complementary results will be discussed and an explanation of the failure mechanism will be presented as the root cause issue, allowing defining the defective step in production process.     

Qualification of bumping processes: Experimental and numerical investigations on mechanical stress and failure modes induced by shear test

In the past few years, novel assembly schemes, such as Flip Chip, 3D assemblies, and advanced low-k/ultralow-k dielectric materials have been introduced in the semiconductor industry. Aiming to develop and grant maturity milestones, standardized procedures are used to assess the assembly reliability. Among them, bump shear test provides a quantitative measure of the bonding strength between the Bump, UBM and pad structure. In this paper, some investigations on the failure mechanism induced by shear test are proposed. At first, it is shown experimentally that, for similar structures, the failure mode depends on the shear tool standoff. More precisely, high height values promote the cratering mode (i.e. fracture in the interconnect layers) whereas low ones induce a ductile mode (i.e. fracture in the bulk Aluminum layer). A numerical model is carried out to provide a better understanding of the mechanisms. Finite element simulations highlight a strong variation of the peeling stress according to the shear height, whereas the shear stress component remains quite stable. Based on these experimental and numerical findings, distinct scenarii and criterion are proposed to explain the fails. This approach is consolidated by extending the comparisons with additional experimental results. At last, the preliminary results of a time dependent study (effect of the shear tool speed and a non linear copper law) are discussed. These first insights aim at giving additional input on the physics occurring during the test.The present work proposes a validated numerical basis to explain and forecast the failure mode preference during a bump shear test. This provides some clues for design guidelines, process integration and product developments.     

基于贝叶斯网络的复杂系统FMEA模型

贝叶斯网络用因果关系图的形式表达变量间相互关系,实现复杂系统的故障模式和效应分析.贝叶斯网络建模先确定模型变量,根据变量间因果关系确定网络的拓扑结构.再为贝叶斯网络赋值,确定先验概率和条件概率.并通过融合新的试验信息与专家信息,改进网络结构,作最后的统计推断.     

某分离用固体小火箭工作故障分析及设计改进

为解决某分离用固体小火箭在高温55℃环境试验中,出现壳体失强与较高点火压力峰的问题,分析了发生该工作故障的可能原因。通过对装药结构及挡药板结构进行改进设计,以期扩大燃气通道;通过对点火药盒结构进行改进设计,并调节点火药药量,以期降低点火压力峰值。验证试验表明,改进措施切实有效,点火压力峰值满足设计要求,提高了小火箭工作的可靠性与安全性。     

企业设备绩效激励工作失效的原因研究与分析

从分析企业设备绩效激励失效的成因出发,借鉴和运用西方的激励理论,对设备绩效考核存在的问题进行了较为系统的研究与分析。对企业设备激励工作失效的原因进行较为详细而系统的分析且运用激励理论提出一种适合企业发展的新型激励机制。     

CMOS／SOSCC4066器件的可靠性研究

本文介绍了CMOS/SOS CC4066器件长期可靠性试验结果。对失效器件的分析表明,硅-蓝宝石技术没有新的失效机理。该器件的可靠性不低于国内体硅MOS IC能达到的水平,并接近“七专”器件的水平。     

铜工艺电迁移分模式失效机理研究

在大规模集成电路进入深次微米时代的同时,铜工艺技术也被广范应用在金属互连层的工序当中。电迁移（Electromigration,EM）测试是检测金属互连层性能的主要方法,本文针对测试结果所呈现的分模式（Bi-modal）现象,对大量累积的测试数据以及物理失效分析的结果进行分析,并且结合对铜工艺的分析,给出了失效机理的解释并以图形化的形式进行了整合归纳。提供了一种快速的通过失效时间进行失效模式分析的方法,为我们不依靠物理失效分析而快速发现工艺问题提供了可能。