Hierarchical Delay Test Generation

Delay testing is used to detect timing errors in a digital circuit.In this paper, we report a tool called MODET forautomatic test generation for path delay faults in modular combinational circuits. Our technique usesprecomputed robust delay tests for individual modules to computerobust delay tests for the module-level circuit. We present alongest path theorem at the module level ofabstraction which specifies the requirements for path selectionduring delay testing. Based on this theorem, we propose a pathselection procedure in module-level circuits and report efficientalgorithms for delay test generation. MODET hasbeen tested against a number of hierarchical circuits with impressivespeedups in relation to gate-level test generation.     

A Test Methodology for High Performance MCMs

Satellite and avionics applications represent an ideal application for the tremendous performance, cost, space, andreliability benefits of MCMs. These advantages are only realized,however, if accompanied by an efficient test strategy whichverifies defect-free fabrication. This paper describes a methodology developed to test high performance VLSI CMOS ICs thathave been mounted onto a multi-chip silicon substrate. A teststrategy, which addresses testing from the wafer level through tothe populated substrate, is detailed. This strategy uses acombination of LSSD, AC LSSD-On-Chip Self Test, Deterministic Delay Fault Testing, and Design for Partitionability to ensure high testquality at a reasonable cost. The methodology is then contrastedto alternative approaches.     

A HIGH RESOLUTION TIME DELAY ESTIMATION BASED ON THE MAXIMUM ENTROPY POWER SPECTRUM ESTIMATON

Multipath time delay estimation is constrained by the width of the signal correlation function when using correlation based methods. This paper obtains a high resolution time delay estimation by introducing Burg algorithm and Marple algorithm of the maximum entropy power spectral estimation to non-resolvable multipath time delay estimatoin. The principles, the performaces and the results of computer simulation are given.     

单频GPS导航定位中的电离层延迟改正方法

电离层延迟是单频ＧＰＡ导航定位的主要误差源之一。本文提出了一种利用单频ＧＰＳ接收伪码载波相位实时观测数据实时估计和改正电离层延迟的方法，着重阐述了利用局部电离层垂直延迟模型和实时观测数据确定载波相位整周模糊度的步骤，并讨论了该电离层改正方法的优缺点和应用前景。     

地震数据采集系统延迟时间研究与分析

文章分析了影响地震采集系统延迟时间的因素,并根据系统延迟的理论对产生的原因进行了论证.同时对实际生产中的测试方法进行了阐述研究和分析,提出了新的测试方法,并结合实际生产提出了合理性建议.     

基于对比折射法的三维静校正技术及其应用

在地形起伏剧烈、速度和厚度横向变化大的地区，折射静校正技术的应用受到诸多限制，主要表现在不能准确地识别和拾取来自于地下连续地质界面的折射波，使得精确求取的长波长静校正量困难。为此，提出了一种基于对比折射法的三维静校正技术。介绍了这种静校正技术的方法原理和特点，基于对比折射法的折射波至拾取实质上是一个折射层的对比分析解释过程，因此能准确地拾取折射波至，精确地求解低速带的绝对延迟时；然后利用延迟时和近地表速度模型（等效，时深，空变）反演表层模型，最终一次性完成基准面静校正（包含低速带校正和高程校正）。在黄土塬、沙漠以及沙漠和山地的接合部等地区，利用基于对比折射法的三维静校正技术进行静校正处理，使资料的品质得到了明显改善，反射同相轴连续性好，信噪比和分辨率高，构造形态清晰可靠，提高了勘探精度。     

转换波延迟时静校正

为了克服传统转换波静校正方法应用效果不佳的缺点,本文介绍一种转换波延迟时静校正方法,此法根据转换波勘探时垂直分量记录的纵波近地表模型及水平分量记录的初至时与纵波分量的初至时之差,求取转换波延迟时,并根据转换波延迟时建立横波的近地表模型,从而求取接收点的横波静校正量。文中给出了转换波延迟时静校正量的计算公式,并用实际地震数据进行了检验。结果表明此法应用效果较好,可以推广应用。目前该静校正方法已经集成到KLSeis采集软件中。     

引信点目标视频回波模拟器距离模拟电路设计

针对某伪码调相PD引信点目标视频回波模拟器的要求,提出了基于现场可编程门阵列（FPGA）与片外精密数控可编程延时线两级延时技术的引信点目标视频回波模拟器距离模拟电路的设计及实现方案。该距离模拟电路具有调整动态范围大、精度高等特点。调试表明,该电路能够满足精密测试引信截止距离的要求。     

激光标刻误差的实验研究

在开发激光打标软件的过程中,针对出现字符笔画残缺、变形、拐角深度标刻等现象,提出了多种延时措施以及改进插补算法等的解决办法.     

Performance analysis of prioritized parallel transmission MAC protocol in all‐IP wireless WAN

Prioritized parallel transmission MAC (PPTM) protocol is proposed for all‐IP wireless wide area network (WAN). In this paper, we analyse its performance and compare it with modified channel load sensing protocol (MCLSP). We model PPTM as a non‐preemptive priority queueing system and obtain a close form of transmission time delay for each priority class, throughput of the scheme, and number of packets in the queue in the Poisson arrival case. We find that PPTM achieves less transmission time delay than MCLSP does for high priority data. Hence, the overall performance of the system using PPTM is significantly improved. We verify the conclusions with simulation via a simplified all‐IP wireless WAN. Copyright © 2006 John Wiley & Sons, Ltd.