A Simon Effect in Pigeons.

Pigeons pecked left versus right keys contingent upon the color presented at 1 of those locations. Spatial-response latencies were shorter when the color appeared at the same location as the required response than at the opposite location. This Simon effect occurred when the stimulus on the alternative key was constant, varied from trial to trial, or changed when the color cue appeared and when the reinforcement probability for correct responses was the same on corresponding as on noncorresponding trials. Humans performing the same task by touching the keys also showed the Simon effect. These findings demonstrate that for pigeons, too, a relevant symbolic cue activates a spatial code that produces faster responses at the location corresponding with the activated code. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

预取技术研究进展

World Wide Web(WWW) services have grown to levels where significant delays are expected to happen.Technology like prefetching are likely to help users to personalize their needs ,reducing their waiting times. This paperfirstly describes the architecture of prefetching,then classifies them into three types: based on branch model,based ontree model and others and presents profoundly the basic ideas of some existing prefetching algorithms. Next,several models for controlling the prefetching are introduced. At last,the trend and course concerning the prefetching algo-rithms are concluded.     

一种新的多线程实现技术

本文提出了一种实现多线程机制的简单有效的新方案，它利用多机系统中原有的Ｃａｃｈｅ实现多线程功能，在很低的代价下实现了多机系统的多线程化，使应用程序的执行效率得到大幅度提高。     

网络处理器体系结构分析

随着网络的发展，网络处理器在构建未来网络系统中发挥着越来越重要的作用。在网络处理器产生的历史背景的基础上，分析了评价其硬件体系结构的主要方面，研究了几种典型的网络处理器的体系结构，总结了网络处理器的总体体系结构特点，阐述了其现有体系结构的发展及下一步的工作。     

面向与历史无关造型的三维约束求解方法研究

以基于历史的造型系统中应用较为成熟的两项技术——特征编码和二维约束求解为基础，基于特征进行三维约束建模，从而打破传统的基于历史造型系统中特征之间的单向依赖关系；然后将三维约束关系映射到二维草图进行处理，简化了问题．该方法在InteSolid 2．0上实现．     

"神五"飞天引发的术语学思考

“神舟”五号载人飞船的发射成功，给术语学研究带来许多有益的思考。首先，重大事件对术语定名的形成具有重要的推动作用。第二，同义术语在一定的历史时期会出现较为明显的分工。第三，学科发展的地域差异通常决定术语的借用走向。实力造就语言，也在很大程度上打造术语。     

Comparison of Operant Escape and Innate Reflex Responses to Nociceptive Skin Temperatures Produced by Heat and Cold Stimulation of Rats.

In behavioral tests, rats performed learned escape responses to thermal stimulation of the paws by 44.0. 47.0. or 0.3 degrees C. Licking, guarding, and jumping reflexes were evaluated at these temperatures. The frequency, latency, and duration of escape and reflex responses were compared and were related to hind-paw skin temperatures measured during stimulation of awake and anesthetized rats. The duration and latency of escape from heat were appropriately related to stimulus intensity. Escape occurred reliably for each intensity. Reflexes occurred unreliably and at long latency to 44.0 or 0.3 degrees C and were not appropriately related to heat intensity. The reflexes were relatively insensitive to thermal nociceptive stimulation other than heating of the skin at a high rate. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

Eyewitness Identification Accuracy and Response Latency: The Unruly 10-12-Second Rule.

Data are reported from 3,213 research eyewitnesses confirming that accurate eyewitness identifications from lineups are made faster than are inaccurate identifications. However, consistent with predictions from the recognition and search literatures, the authors did not find support for the "10-12-s rule" in which lineup identifications faster than 10-12 s maximally discriminate between accurate and inaccurate identifications (D. Dunning & S. Perretta, 2002). Instead, the time frame that proved most discriminating was highly variable across experiments, ranging from 5 s to 29 s, and the maximally discriminating time was often unimpressive in its ability to sort accurate from inaccurate identifications. The authors suggest several factors that are likely to moderate the 10-12-s rule. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

网络处理器体系结构分析

该文旨在分析网络处理器能够同时满足高性能和灵活性要求的体系结构。而传统的网络设备单纯采用专用芯片或者基于RISC的通用处理器(GPPs),很难兼顾这两者要求。该文根据网络处理器的处理空间,将其映射为5个逻辑模块,这些模块由网络处理器中各个功能部件实现。然后分析了网络处理器的SMP和Pipeline两种并行结构,并进一步分析了隐藏延迟等实现加速的技术。最后分析了网络应用发展变化对网络处理器体系结构设计的挑战,并提出了解决办法。     

Execution History Guided Instruction Prefetching

The increasing gap in performance between processors and main memory has made effective instructions prefetching techniques more important than ever. A major deficiency of existing prefetching methods is that most of them require an extra port to I-cache. A recent study by Rivers et al. [19] shows that this factor alone explains why most modern microprocessors do not use such hardware-based I-cache prefetch schemes. The contribution of this paper is two-fold. First, we present a method that does not require an extra port to I-cache. Second, the performance improvement for our method is greater than the best competing method BHGP [23] even disregarding the improvement from not having an extra port. The three key features of our method that prevent the above deficiencies are as follows. First, late prefetching is prevented by correlating misses to dynamically preceding instructions. For example, if the I-cache miss latency is 12 cycles, then the instruction that was fetched 12 cycles prior to the miss is used as the prefetch trigger. Second, the miss history table is kept to a reasonable size by grouping contiguous cache misses together and associated them with one preceding instruction, and therefore, one table entry. Third, the extra I-cache port is avoided through efficient prefetch filtering methods. Experiments show that for our benchmarks, chosen for their poor I-cache performance, an average improvement of 9.2% in runtime is achieved versus the BHGP methods [23], while the hardware cost is also reduced. The improvement will be greater if the runtime impact of avoiding an extra port is considered. When compared to the original machine without prefetching, our method improves performance by about 35% for our benchmarks.