结合试飞特点,开展专用测试设备计量确认

根据我院专用测试设备计量确认现状及需求，对开展试飞专用测试设备计量确认工作的要求，步骤、确认原则，以及编定计量确认方法进行了必要的讨论分析。     

Model validation and model structure determination

This paper gives a tutorial overview of basic approaches for model validation and model structure determination.Work partially supported by the Swedish Research Council for Engineering Sciences under contract 98-654.     

砂基中泥浆盾构法隧道施工开挖面稳定性试验研究

 通过模型试验，对泥浆盾构施工中泥浆维持开挖面稳定的力学机理，开挖面前缘土体的应力变化规律，泥浆压力作用机理及泥皮形态进行了研究，提出了中粗砂地基中临界泥浆压力 公式。     

后压浆技术在杨凌国际会展中心基桩工程中应用效果的分析

本文叙述了杨凌国际会展中心基桩静力载荷试验的试验过程 ;通过对三根灌注桩承载力的试验结果分析 ,认为后压浆技术对提高灌注桩单桩极限承载力有很大作用     

三维叠前深度偏移处理技巧与应用

结合研究区的地质资料，着重就研究区的速度深度模型的人工控制进行了研究；基于研究区断裂系统复杂，为了解所用处理方法对复杂构造的适用性，设计了2个模型来检验叠前深度偏移效果的有效性；与时间偏移相比，叠前深度偏移高质量地解决了复杂断块区的成像问题。     

峡口水库沥青混凝土面板的施工与试验

以灌溉、防洪为主的峡口水库大坝，为沥青混凝土面板堆石坝，为研究低温抗裂性能，对沥青混凝土面板破损取样，进行了配比和多种力学性能试验，并与原面板设计指标进行了对比。由于面板经受住了－20℃以下的低温考验，其所用沥青指标、破损取样试验结果，特别是冻断低温指标，对确定水工沥青混凝土低温抗裂检验标准有重要参考价值。     

砂砾岩储集层含油性解释方法

LJ地区砂砾岩地层具有岩石结构复杂，储集层非均质性强，稠油和稀油并存的特点，利用测井资料解释含油性难度很大，以地层测试资料为依据，综合利用多种测井信息，提取反映含油性变化的测井特征参数；应用测井参数交会法和测井相分析法建立有效，快速识别稠油，油层和水层的标准，测井相分析法消除了用测井单参数和两参数交会解释含油性存在的多解性，提高子解释结果的成功率，用编制的解释软件处理了LJ地区58口井的资料，解释结果与试油资料对比吻合程度较高，为砂岩储层含油性解释提供了一种有效，快速的方法，为该区先导性试验提供了可靠的依据。     

电视机监督检验电磁兼容结果分析和对策

本文讨论了电磁兼容对电视机的技术要求和相应对策。     

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.