测试(试井)成果影响因素浅析

随着测试技术的发展、测试质量及资料解释水平的提高，测试（试井）成果的可靠程度越来越受到重视。影响解释成果的环节和因素很多，从客观和主观两方面分析其主要因素，找出症结所在，从而完善现场环节，完善资料解释过程，提高测试技术及解释水平。     

用改进的ISA方法消除井筒存储效应影响

针对井筒存储效应对ISA（Inverse Solution Algorithm）试井分析方法的影响，利用拉普拉斯反褶积法对实际试井资料进行处理。用地层的变流量过程代替井筒存储效应，对同时测得的井底压力和流量，使用拉普拉斯反褶积方法求出所需要的准确的压力导数，达到消除井筒存储效应的目的；如果不能够同时测得井底的压力和流量，在拉普拉斯反褶积过程中，把井筒存储系数始终当成一个常量来考虑，并以该存储系数来定义变化的流量，然后用拉普拉斯反褶积积分法处理井筒压力和流量，得到压力响应，再通过Stehfest算法将解转换到实空间，这样处理后得出的压力导数结合ISA方法算得的渗透率分布更符合真实的地层情况。该法有助于提高有井筒存储效应影响的实际试井资料分析的准确性。图4表1参12     

钻杆磁记忆无损检测装置研究

针对钻杆的结构与应用环境特点,制定了钻杆磁记忆无损检测装置的设计原则。以笔记本电脑为中心,拟定了以霍尔传感器和光电编码器检测钻杆应力集中隐性缺陷及其位置的方案。根据钻杆的结构特点。设计了探头距离可调的适用于圆钻杆和方钻杆的探测小车。基于面向对象的程序设计思想．利用VC＋＋6．0语言开发了相应检测分析软件。重点介绍了所用的数据处理技术。现场检测试验表明该装置不仅能有效地检测钻杆应力集中。且可以对应力集中程度进行评估,对预防钻杆突发失效事故可起到较好的预防作用。     

利用注水井测试资料识别油层高渗透带

对于已进入高含水后期的水驱油田而言,控水是延长油田有效开发期,提高油田寿命的必由之路,而高含水后期水驱控水重点是针对导致注入水低效无效循环的高渗透带,因此必须开展高渗透带的识别,进而使水驱控水措施有的放矢,为高含水后期的水驱控水提供技术支撑。本文从高渗透带的基本特征出发,应用其在测井资料上的鲜明特征结合动静态等资料加以识别,并开展了应用,其效果表明应用测井资料识别高渗透带油层是可行的。     

夹持式扭矩传感器

针对目前录井现场各类在用扭矩传感器存在的安装方便性、精度、稳定性和耐用性差等不足,开发研制了新型夹持式扭矩传感器。在简要分析在用扭矩传感器的优缺点基础上,重点介绍了夹持式传感器的测量原理和电路、样机测试结果及产品特点。与在用各类扭矩传感器相比,夹持式扭矩传感器不仅具有设计思路新颖、重量轻、安装方便、使用寿命长、测量灵敏度高等特点,而且能够获得真扭矩值,可为分析井下钻具工况提供十分有价值的参数。样机测试结果表明,其检测精度高,可靠性好。     

油井自动分层测试开关工具设计及应用

通过对高含水油井的分层测试,可以准确找到出水层,为堵水作业提供依据。设计了一种分层测试开关工具,与封隔器、丢手等组成分层测试管柱。现场试验表明,该测试开关动作可靠,可实现油井的找水及分层测试作业,满足现场生产需要。     

ROV扭矩工具系统研制与应用

ROV扭矩工具(TT)是深水水下油气田开发过程中使用的水下机器人(ROV)作业装备。ROV扭矩工具系统是以ROV为核心,包括扭矩工具本体和控制系统,其结构尺寸和工作能力与工作效率是影响水下作业的便利性与作业成本的关键因素。依托南海某气田水下生产系统,参考ISO13628-8等规范,设计出具有多尺寸自适应接口、牙嵌离合换挡结构和锁紧机构的扭矩工具及其控制系统。采用有限元分析软件对扭矩工具关键部件进行仿真分析。完成了扭矩工具的样机研制并进行测试。测试结果表明：水下ROV扭矩工具的锁紧、解锁功能,换挡功能,马达闭环控制功能均可实现,技术参数满足设计要求。研究成果对ROV扭矩工具及其控制系统的技术发展和产品开发均有借鉴意义。     

Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits

In this paper, we present an exhaustive study on the influence of resistive-open defects in pre-charge circuits of SRAM memories. In SRAM memories, the pre-charge circuits operate the pre-charge and equalization at a certain voltage level, in general Vdd, of all the couples of bit lines of the memory array. This action is essential in order to ensure correct read operations. We have analyzed the impact of resistive-opens placed in different locations of these circuits. Each defect studied in this paper disturbs the pre-charge circuit in a different way and for different resistive ranges, but the produced effect on the normal memory action is always the perturbation of the read operations. This faulty behavior can be modeled by Un-Restored Write Faults (URWFs) and Un-Restored Read Faults (URRFs), because there is an incorrect pre-charge/equalization of the bit lines after a write or read operation that disturbs the following read operation. In the last part of the paper, we demonstrate that the test of URWFs is more effective in terms of resistive defect detection than that of URRFs and we list the necessary test conditions to detect them.

Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing

In this paper we propose a new approach to generate a primary input blocking pattern for applying to the primary inputs during shift cycle such that the switching activity occurred in the combinational part of the circuit under test can be suppressed as much as possible. The primary input blocking technique suppresses transitions of gates in the combinational part during scan by assigning controlling values to one of the gates' inputs. However, simultaneously assigning controlling values to the gates may result in conflicts in the setting of binary values on the primary inputs. Instead of the heuristics based on fanout in other approaches, we use the impact function which is based on transition density to determine the priorities of the gates to be blocked. Experiments performed on the ISCAS 89 benchmark circuits show that the proposed approach can always produce better results than the existing approaches.

A Graph-Based Approach to Power-Constrained SOC Test Scheduling

The test scheduling problem is one of the major issues in the test integration of system-on-chip (SOC), and a test schedule is usually influenced by the test access mechanism (TAM). In this paper we propose a graph-based approach to power-constrained test scheduling, with TAM assignment and test conflicts also considered. By mapping a test schedule to a subgraph of the test compatibility graph, an interval graph recognition method can be used to determine the order of the core tests. We then present a heuristic algorithm that can effectively assign TAM wires to the cores, given the test order. With the help of the tabu search method and the test compatibility graph, the proposed algorithm allows rapid exploration of the solution space. Experimental results for the ITC02 benchmarks show that short test length is achieved within reasonable computation time.