一种8-b 180KSPS的带有新颖的时域比较器且有效位数7.97的差分逐次逼近模数转换器

This paper presents a differential successive approximation register analog-to-digital converter (SAR ADC) with a novel time-domain comparator design for wireless sensor networks. The prototype chip has been implemented in the UMC 0.18-μ m 1P6M CMOS process. The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz. With the Nyquist input frequency, 68.49-dB SFDR, 7.97-ENOB is achieved. A simple quadrate layout is adopted to ease the routing complexity of the common-centroid symmetry layout. The ADC maintains a maximum differential nonlinearity of less than 0.08 LSB and integral nonlinearity less than 0.34 LSB by this type of layout.     

16位流水线ADC系统级建模及仿真

基于MATLAB/Simulink的平台,设计并实现了16bit 100M流水线模数转换器(ADC)系统仿真的理想模型.在充分掌握流水线ADC整体结构基础上,对其基本模块进行建模,充分考虑并加入电路的非理想特性和噪声,使整个系统模型接近实际电路.在输入信号为40MH2,采样时钟频率为100MHz时,分别对理想模型和加入非理想因素后的模型进行仿真比较,得到各项性能指标.对实际电路的设计具有一定的借鉴作用.     

A power scalable PLL frequency synthesizer for high-speed △-∑ ADC

A 35-130 MHz/300-360 MHz phase-locked loop frequency synthesizer for △-∑ analog-to-digital con- verter （ADC） in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode （300-360 MHz） or in low-power mode （35-130 MHz） to satisfy the ADC＇s requirements. To switch between these two modes, a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the fre- quency synthesizer achieves a phase-noise of-132 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of-112 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 7.23 ps with 0.92 mW power consumption from a 1.2 V power supply.     

An ll-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation

Abstract： This paper presents an l 1-bit 22-MS/s 0.6-mW successive approximation register （SAR） analog-to- digital converter （ADC） using SMIC 65-nm low leakage （LL） CMOS technology with a 1.2 V supply voltage. To reduce the total capacitance and core area the split capacitor architecture is adopted. But in high resolution ADCs the parasitic capacitance in the LSB-side would decrease the linearity of the ADC and it is hard to calibrate. This paper proposes a parasitic capacitance compensation technique to cancel the effect with no calibration circuits. Moreover, dynamic circuits are used to minimize the switching power of the digital logic and also can reduce the latency time. The prototype chip realized an 11-bit SAR ADC fabricated in SMIC 65-nm CMOS technology with a core area of 300 × 200 μm2. It shows a sampling rate of 22 MS/s and low power dissipation of 0.6 mW at a 1.2 V supply voltage. At low input frequency the signal-to-noise-and-distortion ratio （SNDR） is 59.3 dB and the spurious-free dynamic range is 72.2 dB. The peak figure-of-merit is 36.4 fJ/conversion-step.     

A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer in 0.13 μm CMOS

This paper presents a 0.6 V 10 bit successive approximation register （SAR） ADC design dedicated to the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified through both simulation and measurement results. Fabricated with 1P8M 0.13 μm CMOS technology, the proposed SAR ADC consumes 6.3 μW at 1 MS/s from a 0.6 V supply, and achieves 51.25 dB SNDR at the Nyquist frequency and FOM of 21 fJ/conversion-step. The core area is only 120 × 300 μm^2.     

AD9520高速时钟发生器在5Gs/s数据采集系统中的应用

随着高速数据采集系统的快速发展及其复杂性提高,其关键部分高速ADC(Analog to Digital Converter,模/数转换器)对时钟质量的要求也越来越高,为此提出了一种基于内部集成2.5 GHz VCO(压控振荡器)的低相位噪声锁相环时钟芯片AD9520[1]的高质量时钟电路设计,介绍了在5 Gs/s高速数据采集系统中AD9520的具体设计应用,包括其控制寄存器的参数配置以及初始化顺序等,给出了该高速数据采集系统的原理框图,并采用Xilinx公司ISE软件中的在线逻辑分析仪(ChipScope Pro)测试了时钟性能,实测表明整体指标达到设计要求。     

新产品＆新技术

Tensilica全球发布四款视频处理引擎；ADI公司的低功耗ADC支持医学和工业电子设备；ADI公司Blackfin处理器ADSP—BF54x系列产品；Microchip推出内置分流稳压器的PIC单片机；[编者按]     

12与14位210MS／s ADC

德州仪器推出与ADS5546引脚兼容的12、14位ADC ADS5547与ADS5527，能够在采样速率为210MS／s、输入频率为70MHz的情况下提供高达73．3dBFS的信噪比（SNR）和85dBc的无杂散动态范围（SFDR）。为雷达与成像技术提供更大的范围和更高的分辨率，为数字预失真解决方案提供更精确的功率放大器，实现更高质量的视频与影像系统。     

具有片上多段基准源的14位宽温度范围高SNDR全差分逐次逼近型模数转换器

介绍了一种带有片上多段带隙基准源的14位低功耗自定时全差分逐次逼近型模数转换器。采用一个在-40到120℃温度范围内具有1.3ppm/℃温度系数的片上多段带隙基准电压源来为逐次逼近型模数转换器提供高精度基准电压源。设计中用格雷码代替二进制编码来减少衬底噪声从而增加整个系统的线性度。采用自定时位循环来增加时间利用率。该14位模数转换器利用TSMC 0.13μm CMOS工艺流片。该逐次逼近型模数转换器在室温2M/s 转换速率条件下能够获得81.2dB SNDR (有效位数13.2) 和85.2dB SFDR,并且在2M/s转换速率下在-40到120℃温度范围内能够保持12位以上有效位数。     

高速低功耗的16位ADC

ADS1601与ADS1602针对线性度较高的高速操作进行了优化，功耗由外部电阻器设定，通过专用同步引脚实现多个器件在多通道系统中同时进行采样。ADS1602的采样频率为40MSPS，而数字滤波器则将调制器输出降低至1／16，以便通过串行接口提供速率为2．5MSPS、16位分辨率的输出数据，可提供1．23MHz的带通转换能力，总谐波失真(THD)小于-101dB，