H.264 video transmissions over wireless networks: Challenges and solutions

Multimedia video streaming is becoming increasingly popular. Using multimedia services, there are more and more users in end-system over wireless networking environment. H.264/AVC is now the standard for video streaming because of its high compression efficiency, robustness against errors and network-friendly features. However, providing the desired quality of service or improving the transmission efficiency for H.264 video transmissions over wireless networks present numbers of challenges. In this paper, we consider those challenges and survey existing mechanisms based on the protocol layers they work on. Finally, we address some open research issues concerning for H.264 video transmission in wireless networks.     

A study of 3D Network-on-Chip design for data parallel H.264 coding

In this paper, we implement, analyze and compare different Network-on-Chip (NoC) architectures aiming at higher efficiencies for MPEG-4/H.264 coding. Two-dimensional (2D) and three-dimensional (3D) NoCs based on Non-Uniform Cache Access (NUCA) are analyzed. We present results using a full system simulator with realistic workloads. Experiments show the average network latencies in two 3D NoCs are reduced by 28% and 34% respectively, comparing with 2D design. It is also shown that heat dissipation is a trade-off in improving performance of 3D chips. Our analysis and experiment results provide a guideline to design efficient 3D NoCs for data parallel H.264 coding applications.     

Motion mapping and mode decision for MPEG-2 to H.264/AVC transcoding

This paper describes novel transcoding techniques aimed for low-complexity MPEG-2 to H.264/AVC transcoding. An important application for this type of conversion is efficient storage of broadcast video in consumer devices. The architecture for such a system is presented, which includes novel motion mapping and mode decision algorithms. For the motion mapping, two algorithms are presented. Both efficiently map incoming MPEG-2 motion vectors to outgoing H.264/AVC motion vectors regardless of the block sizes that the motion vectors correspond to. In addition, the algorithm maps motion vectors to different reference pictures, which is useful for picture type conversion and prediction from multiple reference pictures. We also propose an efficient rate-distortion optimised macroblock coding mode decision algorithm, which first evaluates candidate modes based on a simple cost function so that a reduced set of candidate modes is formed, then based on this reduced set, we evaluate the more complex Lagrangian cost calculation to determine the coding mode. Extensive simulation results show that our proposed transcoder incorporating the proposed algorithms achieves very good rate-distortion performance with low complexity. Compared with the cascaded decoder-encoder solution, the coding efficiency is maintained while the complexity is significantly reduced.

H.264宏块选择的自适应算法研究

在视频编码的过程中,运动估计占据了举足轻重的地位.其性能优劣会在一定程度上决定了码流质量.采用16×16宏块能够提高压缩比,但容易产生方块效应,使用4×4宏块可以提高图像质量,但降低了压缩比。H.264视频压缩标准采用多模式运动估计,可以有效减少块匹配预测误差,但随着模式的增多,算法计算量成倍增加.为了克服这个困难,本文提出一种新的自适应的宏块划分和运动估计算法。这种分块算法在综合考虑图像本身特性在编码过程中,根据图像的各个部分运动程度不同而采用不同的分快策略,兼顾图像质量和处理开销。     

基于JPEG的固定背景视频压缩算法研究

为了对固定背景视频进行压缩并获得较高的压缩比,在JPEG静止图像压缩标准的基础上提出了一种新的应用于固定背景视频压缩的算法.对第一帧图像进行JPEG格式的压缩并保存量化后的离散余弦变换系数,对第一帧后的每一帧图像,在进行离散余弦变换和量化后,先同存储器内的第一帧图像的离散余弦变换系数进行异或运算再进行熵编码.通过使用该算法和H.264视频压缩标准对同一段固定背景视频进行压缩并比较压缩后的数据量,表明了该算法具有较高的压缩比.     

VNC多媒体数据实时传输的研究与实现

针对VNC在传输多媒体数据时高带宽、低帧率的缺陷,在分析现有的编码方法和混合远程显示协议的基础上,提出了一种启发式方法一局部压缩法.该方法通过统计像素点的像素值变化频率,检测出桌面上的高频区域,并使用H.264编码该高频区域,对于桌面上的其它低频区域仍然采用VNC原有的编码方法.实验结果表明,该方法能够达到视频流畅播放所要求的帧率,同时能够有效地降低了网络带宽和CPU利用率.     

基于2D Cache结构的H.264运动补偿访存带宽优化方法

H.264/AVC的运动补偿处理环节需要消耗大量的内存访问带宽,这成为制约其性能的关键因素.分析表明,如此巨大的带宽消耗具体来自5个方面:像素数据的重复读取、地址对齐、突发访问、SDRAM页切换和内存竞争冲突.提出一种基于2D Cache结构的运动补偿带宽优化方法,充分利用像素的重用以减少数据的重复读取.同时通过结合数据在SDRAM中映射方式的优化,将众多短而随机的访问整合为地址对齐的突发访问,并减少了访问过程中页切换的次数.此外还提出了访存的组突发访问模式,以解决SDRAM竞争冲突所引入的开销.实验结果表明采用上述优化设计后,运动补偿的访存带宽降低了82.9～87.6%,同现存优化效率较高的方法相比,带宽进一步减少了64%～87%.在达到相同带宽减少幅度的前提下,所提出的新方法比传统Cache结构电路面积减少91%.该方法目前已在一款多媒体SoC芯片设计中实际应用.     

基于功能和数据划分的H.264并行解码算法

针对H.264视频解码算法的并行模块选择、划分及解码速度优化等问题,面向TilePro64多核平台,提出一种可扩展的H.264并行解码算法。对该算法的内部功能模块进行整合和划分,根据核间数据的依赖关系,动态分配功能模块及优化算法并行效率。实验结果表明,该算法在解码效率、多核并行程度、解码时延等方面均有较好性能,相比传统并行解码算法,其并行加速比提高约25%。     

AVS及H.264双模可变长解码器设计

为使视频解码芯片能同时兼容AVS及H.264这2种视频编码标准,设计一种双模可变长解码器。该设计复用码流缓冲移位和指数哥伦布解码模块,采用组合逻辑电路查找码表,对AVS和H.264码表进行优化与重组。在ModelSim环境下完成仿真测试,并通过FPGA芯片进行综合验证。结果表明,该设计能有效支持AVS和H.264 2种标准,减小电路资源消耗和面积,并提高查找表的查找效率。     

基于FPGA的H.264帧内预测实现和优化

在使用硬件电路进行H.264编码时,为提高帧内预测运算速度,减少硬件电路面积,提出一种基于现场可编程门阵列(FPGA)的H.264帧内预测硬件电路的实现和优化解决方案。利用FPGA的并行处理能力和同模式下帧内预测数据冗余对硬件电路进行优化。使用Verilog语言进行模块设计,仿真平台为Modelsim,在Altera CycloneII EP2C20F484C上的实现,验证了该硬件电路结构的高效性及实用性。