Robust spatio-temporal error concealment for packet- lossy H.264 video transmission

1 Introduction With the ubiquitous use of Internet and the deployment of next generation of networks, video communications are increa- singly becoming the major services in demand. Unlike data transmission, video communication is essentially time-sensitiv…     

A Fast Intra Skip Detection Algorithm for H.264/AVC Video Encoding

A fast intra skip detection algorithm based on the rate‐distortion (RD) cost for an inter frame (P‐slices) is proposed for H.264/AVC video encoding. In the H.264/AVC coding standard, a robust rate‐distortion optimization technique is used to select the best coding mode and reference frame for each macroblock (MB). There are three types of intra predictions according to profiles. These are 16×16 and 4×4 intra predictions for luminance and an 8×8 intra prediction for chroma. For the high profile, an 8×8 intra prediction has been added for luminance. The 4×4 prediction mode has 9 prediction directions with 4 directions for 16×16 and 8×8 luma, and 8×8 chrominance. In addition to the inter mode search procedure, an intra mode search causes a significant increase in the complexity and computational load for an inter frame. To reduce the computational load of the intra mode search at the inter frame, the RD costs of the neighborhood MBs for the current MB are used and we propose an adaptive thresholding scheme for the intra skip extraction. We verified the performance of the proposed scheme through comparative analysis of experimental results using joint model reference software. The overall encoding time was reduced up to 32% for the IPPP sequence type and 35% for the IBBPBBP sequence type.     

An improved reversible data hiding-based approach for intra-frame error concealment in H.264/AVC

As H.264/AVC video streams are highly compressed, they become sensitive to errors caused by unreliable transmission channels. In order to address this issue, an improved version of Chung et al.’s reversible data hiding-based approach for intra-frame error concealment is proposed for H.264/AVC codec. By using the histogram shifting technique, the original work reversibly embeds the motion vector (MV) of a macroblock (MB) into other MB within the same intra-frame. If an MB is corrupted at the decoder side, the embedded MV can be extracted from the corresponding MB for the recovery of the corrupted MB. However, Chung et al.’s work did not fully exploit the number of coefficients which need to be modified in order to reversibly hiding data, and did not consider many extra nonzero residual blocks produced by data hiding. These two issues could reduce the visual quality of the stego-video. This paper adopts MV data pre-processing, the selection of most suitable embedding region, and the minimum possible amount of histogram modification, which lead to higher PSNR of the stego-video for a given payload. Experimental results further reveal that the proposed method offers stego-video with better visual quality over Chung et al.’s work.     

基于分形的深度图序列编码算法

充分利用深度图序列相邻帧间的局部相似性,并结合H.264帧内预测编码算法,提出了一种适用于深度图序列编码的新方法,即深度图序列的I帧编码采用H.264帧内预测结构而P帧编码采用基于分形理论的压缩方法。首先介绍了分形编码的理论基础,然后通过改进非均匀多层次六边形格点整像素运动搜索(UMHexagonS)方法,提出了一种更适用于分形编码的基于运动矢量场的自适应六边形搜索算法,从而形成了基于分形的深度图P帧预测编码结构。实验结果表明:本文提出的编码系统在很大程度上提高了H.264的编码性能,峰值信噪比差值(BDPSNR)平均提高了3.54dB,编码比特率差值(BDBR)平均降低40.98%,同时编码复杂度也大大降低,平均编码时间减少了85.27%。     

H.264,VC-1和AVS视频编码研究

从编码结构、核心技术和编码性能等方面对H．264,VC-1和AVS标准进行了研究分析,并综合比较了各个编码技术标准的特点,为应用视频压缩编码标准提供了依据。     

H.264编码技术和发展趋势

自2003年推出H．264视音频编解码标准以来，H．264迅速在Internet网和视音频领域得到普及与推广。阐述H．264的定义、H．264编码技术的主要特点与改进及其应用前景和发展趋势。     

小数运动估计在可重构处理器ReMAP的映射实现

介绍一种在可重构媒体处理器ReMAP上实现小数运动估计的方法.ReMAP处理器由可重构的运算单元阵列和互联单元级联组成,具有高度可重构性和强大的并行计算能力.在ReMAP中映射实现了小数运动估计中的1/2插值、1/4插值和搜索等算法.通过算法的仿真验证分析,ReMAP可支撑小数运动估计的高性能实现,达到或接近ASIC的性能,并具有较好的应用灵活性,适于媒体处理应用.     

A hierarchical design methodology for full-search block matching motion estimation

Many useful DSP algorithms have high dimensions and complex logic. Consequently, an efficient implementation of these algorithms on parallel processor arrays must involve a structured design methodology. Full-search block-matching motion estimation is one of those algorithms that can be developed using parallel processor arrays. In this paper, we present a hierarchical design methodology for the full-search block matching motion estimation. Our proposed methodology reduces the complexity of the algorithm into simpler steps and then explores the different possible design options at each step. Input data timing restrictions are taken into consideration as well as buffering requirements. A designer is able to modify system performance by selecting some of the algorithm variables for pipelining or broadcasting. Our proposed design strategy also allows the designer to study time and hardware complexities of computations at each level of the hierarchy. The resultant architecture allows easy modifications to the organization of data buffers and processing elements-their number, datapath pipelining, and complexity-to produce a system whose performance matches the video data sample rate requirements.     

一种新的IP网络视频通信丢包错误纠正方案

分组丢失是IP交换网络常见的现象。该文针对下一代网络多媒体通信,提出了一套IP网络抗分组丢失的方案。包括纠删编码、打包和发送以及接收端错误掩盖。与常见的纠删编码相比,该文提出的[9,5,3]码具有构造简单,编解码时间短,纠删能力高的优点。打包和发送方案根据[9,5,3]码的纠删性能对视频数据打包,并以一定顺序发送,提高了纠删码抗突发错误的能力。采用新的视频编码方案H.264所提供的抗误码工具灵活的宏块次序(FMO),对纠删失效的视频数据在解码端进行错误掩盖。     

基于BCM3540的高清晰度数字电视机顶盒的硬件设计

介绍一种基于BCM3540的高清晰度数字电视机顶盒的硬件设计方案,该方案采用1块主芯片BCM3540及1块协处理器BCM7411,能够处理MPEG-2高清、标清以及H.264高清、标清信号,可以直接支持PCMCIA接口实现机卡分离,并具有32位PCI总线,可以很方便地进行功能扩展。