An Efficient Architecture for a Lifted 2D Biorthogonal DWT

This paper presents a new algorithm for a 2D non-separable lifted bi-orthogonal wavelet transform. The algorithm is derived by factoring complementary pairs of wavelet transform 2D filters. The results are efficient architectures for real time signal processing, which do not require transpose memory for the 2D processing of data. The proposed architecture exploits in place implementation, inherit from the algorithm, and can take advantage of both vertical and horizontal parallelism in the direct implementation. The processing in our architecture is scheduled by carefully pipelining the lifted steps, which allows for up to four times faster processing than the direct implementation. The proposed architecture operates at high speed, consumes low power and has reduced computational complexity as compared to previously published filter and lifted based bi-orthogonal wavelet architectures.M. Alam (Student) is currently M.Sc. student in the Department of Electrical and Computer Engineering at University of Calgary. His research interest includes VLSI signal processing. He is recipient of iCORE International Graduate Scholarship.Wael Badawy (Ph.D. 00, M.Sc 98, 97; B.Sc. 94) is an associate professor in the Department of Electrical and Computer Engineering. He holds an adjunct professor in the Department of Mechanical Engineering, University of Alberta.Dr. Badawys research interests are in the areas of: Microelectronics, VLSI architectures for video applications with low-bit rate applications, digital video processing, low power design methodologies, and VLSI prototyping. His research involves designing new models, techniques, algorithms, architectures and low power prototype for novel system and consumer products. Dr. Badawy authored and co-authored more than 100 peer reviewed Journal and Conference papers and about 30 technical reports. He is the Guest Editor for the special issue on System on Chip for Real-Time Applications in the Canadian Journal on Electrical and Computer Engineering, the Technical Chair for the 2002 International Workshop on SoC for real-time applications, and a technical reviewer in several IEEE journals and conferences. He is currently a member of the IEEE-CAS Technical Committee on Communication. Dr. Badawy was honored with the 2002 Petro Canada Young Innovator Award, 2001 Micralyne Microsystems Design Award and the 1998 Upsilon Pi Epsilon Honor Society and IEEE Computer Society Award for Academic Excellence in Computer Disciplines. He is currently the Chairman of the Canadian Advisor Committee (CAC) and Head of the Canadian Delegation on ISO/IEC/JTC1/SC6 Telecommunications and Information Exchange Between Systems. Member, The Canadian Advisory Committee for the Standards Council of Canada-Subcommittee 29: Coding of Audio, Picture Multimedia and Hypermedia Information, and Canadian Delegate, The ISO/IEC MPEG standard committee. He is a voting Member on the VSI Alliance. He is also the Chair of the IEEE-Southern Alberta Society-Computer Chapter.Vassil S. Dimitrov was born in Plovdiv, Bulgaria, in 1964. He received his Ph.D. degree in mathematics in 1995 from the Mathematical Institute of the Bulgarian Academy of Sciences. Since then, he has spent two years as a postdocral fellow at the VLSI Research Group, University of Windsor, Canada, one year as a research scientist at the Reliable Software Technology Corporation, Virginia, USA, one year as a chief research scientist at the Signal Processing and Computer Technology Laboratory, Helsinki University of Technology, Finland, and one year as an Associate Professor at the University of Windsor, Canada. Since July 2001 he has held the position of Associate Professor at the Department of Electrical and Computer Engineering, University of Calgary, Canada. His main interests are in the area of number theoretic algorithms, computational complexity, cryptography, optimization theory, fast algorithms for digital signal processing and related topics. Dr. Dimitrov is a member of the New York Academy of Sciences.Graham Jullien (Fellow IEEE) was educated in the United Kingdom, receiving degrees, in Electrical Engineering, from the Universities of Loughborough, Birmingham and Aston (Ph.D., 1969). He was a student engineer and data processing engineer at English Electric Computers, UK, from 1961 to 1966, and a visiting senior research engineer at the Central Research Laboratories of EMI Ltd., UK, from 1975 to 1976. From 1969 until 2000 he was with the Department of Electrical and Computer Engineering at the University of Windsor, Ontario, Canada, where he held the rank of University Professor and was the Director of the VLSI Research Group. Since January 2001, he has been with the Department of Electrical and Computer Engineering at the University of Calgary, where he holds the iCORE Research Chair in Advanced Technology Information Processing Systems. He is a member of the Board of Directors of the Canadian Microelectronics Corporation (CMC) and is a member of the Steering Committee and Board of Directors of the Micronet Network of Centres of Excellence. He has published widely in the fields of Digital Signal Processing, Computer Arithmetic, Neural Networks and VLSI Systems, and teaches courses in related areas. He has served on the technical committees of many international conferences; he currently serves on the Editorial Board of the Journal of VLSI Signal Processing; and is a past Associate Editor of the IEEE Transactions on Computers. He hosted and was program co-chair of the 11th IEEE Symposium on Computer Arithmetic, was program chair for the 8th Great Lakes Symposium on VLSI, and was the technical program chair for the 1999 Asilomar Conference on Signals, Systems and Computers. He is general chair for the 2003 Asilomar Conference and general co-chair of the International Workshop on System-on-Chip for Real-Time Systems, Calgary, Alberta 2003.     

Downlink Dimensioning for the HSDPA Standard

We present an analytic derivation of downlink dimensioning for a wireless network employing the High Speed Downlink Packet Access (HSDPA) standard [Moulsley, Conference Publication No. 477, IEE 2001], currently being developed by the 3rd Generation Partnership Project (3GPP) [http://www.3gpp.org] as part of the next stage in the evolution of the WCDMA standard. We determine the maximum possible cell radius such that the probability of outage, P_out, at the cells worst location does not exceed a preset value under full load condition. The results of the paper are presented in the form of curves obtained by numerical integration of integral expressions. The results can be used, for instance, to find the increase in cell radius achievable by a certain reduction in the threshold value of the Signal to Interference plus Noise Ratio (SINR) defining outage.Parts of this work were presented at the 2002 IEEE Wireless Personal Multimedia Communications conference (WPMC), Hawaii.Dan Avidor was born in Tel Aviv, Israel, on October 18, 1936. He received the B.Sc. degree in electrical engineering from the Technion-Israel Institute of Technology, Haifa, Israel, in 1958 and the M.Sc. and Ph.D. degrees in engineering from the University of California, Los Angeles, (UCLA) in 1970 and 1981, respectively. After completing his studies for the Ph.D. degree, he returned to Israel, where he served as a Research and Development Department Head in the Israeli defense forces. He is currently a Distinguished Member of Technical Staff in the Wireless Research Laboratory, Bell Labs, Lucent Technologies, NJ, USA. His current research interests are in adaptive arrays, signal processing, and simulation techniques for wireless systems.Sayandev Mukherjee (M92) was born in Bangalore, India in 1970. He received the Bachelor of Technology degree in electrical engineering from the Indian Institute of Technology, Kanpur, India, in 1991, and the M.S. and Ph.D. degrees in electrical engineering from Cornell University, Ithaca, NY, in 1994 and 1997, respectively. Since 1996, he has been a Member of Technical Staff in the Wireless Research Laboratory, Bell Labs, Lucent Technologies, NJ, USA. His research interests include stochastic models, wireless system simulations, and intelligent resource allocation in wireless systems.     

基于统计模型的三维场景重建补洞算法

提出了一种新的处理距离图像(即点云数据)算法。算法提取已经获得的表面数据的特性．计算各个被测的特征值,建立马尔可夫统计模型,描述整个表面的数学特征,进而利用最大似然概率预测丢失位置的数据值,得到被测物体表面的完整的数据描述。使用该算法恢复由于障碍物和表面小良反射特性产生的空洞,具有良好的视觉效果．与测量获得的表面数据具有统一的几何特征。     

掺Er3 铅卤碲酸盐玻璃的光谱特性研究

分别以TeO2-PbCl2、ZnO-Na2O和TeO2-ZnO-Na2O为基质制备了掺Er3+铅卤碲酸盐(EDTPb)玻璃和碲酸盐(EDT)玻璃.差热分析(DTA)结果表明,EDTPb玻璃具有更高的热稳定性.应用McCum-ber原理计算的结果表明4 mol%PbCl2的加入可使EDT玻璃在1.53 μm处的发射截面提高6.7%,其峰值达8.79×10-21cm2,而有效宽度从65.8 nm增加到72.3 nm,因此,PbCl2的加入明显改善了玻璃的发光特性.同时应用Judd-Ofelt理论对2种玻璃中Er3+的自发跃迁几率、荧光分支比和能级寿命等光谱特性进行了计算.     

Y2O3:Eu电致发光膜的制备与结构表征

采用电子束蒸发和射频磁控溅射技术沉积了Y2 O3 :Eu电致发光薄膜 ,对膜进行了不同温度的大气热处理。用原子力显微镜 (AFM)观察了Y2 O3 :Eu膜的表面形貌 ,用X射线 (XRD)分析了Y2 O3 :Eu膜的结构 ,并对两种Y2 O3 :Eu膜的微结构和表面形貌进行了比较。结果表明 ,射频磁控溅射Y2 O3 :Eu膜与电子束蒸发Y2 O3 :Eu膜相比 ,结构更致密 ,表面更平滑 ,而且 ,在 90 0°C高温热处理后 ,溅射膜呈现单斜晶系结构 ,具有该结构的Y2 O3 :Eu膜适宜于作电致发光膜。     

三维微流道系统技术研究

采用LTCC技术,可以获得替代采用硅或其他技术制作的微功能结构,简化工艺,降低成本.重点研究了内嵌三维(3D)微流道系统LTCC多层基板成型中的关键技术:热压和烧结,并进行工艺优化.利用优化的热压、烧结工艺参数,可制备出完好的3D微流道系统LTCC多层基板;通过实验验证,LTCC内嵌三维微流道系统取得了良好的散热效果.     

基于针孔阵列的多光束共焦三维测量系统

提出了一种基于 5 0 0× 5 0 0的针孔阵列的多光束共焦三维测量系统 ,该系统具有测量视场大 ,测量速度快 ,系统结构简单等特点     

嵌入式Linux下S3C2410的调色板彩色显示

嵌入式应用中,由于计算能力以及硬件资源的限制,常需要降低颜色深度,以获得较高的分辨率,因此调色板彩色显示是一种很重要的手段。在此以ARM9核的S3C2410芯片为例,探讨分析调色板的概念及配置方法,通过修改驱动程序,实现了调色板彩色显示,给出了编程实例,总结了实现方法。试验表明,当LCD分辨率较高时,采用调色板彩色显示,解决了屏幕抖动和不连贯现象的发生。     

Vivi在便携式心电监护系统设计中的应用

针对心电监护系统在体积、功能、实时性等方面的不足,以S3C2440为中央处理器设计了一款便携式心电监护系统,具有体积小、成本低、功能强、实时性好等特点,并在此基础上研究了Vivi在心电监护系统中的移植。经测试,移植的Vivi在设计的心电监护系统硬件平台上能稳定运行。     

Thermal characteristic of Cu-Cu bonding layer in 3-D integrated circuits stack

Copper (Cu) thermo-compression bonding of wafers can be used to fabricate multi-layer three-dimensional (3-D) integrated circuits (ICs). This work examines the thermal characteristic of the Cu bonding layer and demonstrates experimentally that Cu bonding layer can act as a spreading layer that helps in heat dissipation of bonded 3-D ICs stack more efficiently compared to silicon dioxide bonding layer. The use of Cu bonding layer in a double-layer stack of ICs provides better cooling by as much as 9 °C compared to oxide bonding interface.