Nios SoC系统中的BCH编解码IP核的设计

在编码理论中,BCH码是一种得到深入研究的循环纠错码。SoC(片上系统)设计是电子设计的发展方向。BCH码的SoC实现方法和传统的多片实现方法相比,在工程上具有便捷、小型化及高速等特点。文中分析了使用SoC设计方法完成BCH编解码的设计思路;给出了BCH编码、Berleka-mp译码以及CPU接口的实现细节;同时给出了重要模块的仿真结果。     

一种纠错32位BCH码的硬件实现

针对NANDFlash因制造工艺不断提高而导致其内部数据区随机错误不断增加的现象,传统的8bit,16bit BCH编译码器已难以满足广大客户的需求,现提出了一种新型BCH编译码器结构,所设计的(8640,8192)编码译码器可以在单页数据(1024B)的基础上纠错32bit数据,并在译码电路中,在编码输入电路,伴随式模块与chien搜索模块采取并行算法处理,大大提高了数据的处理速度。     

Analysis and performance evaluation of new coding options for space telecommand links ‐ Part I: AWGN channels

We investigate and compare, over the additive white Gaussian noise channel, different options for updating the error correcting code currently used in space mission telecommand links. Besides some more consolidated proposals, using low‐density parity‐check codes, we characterize and assess the performance of alternative schemes, based on parallel turbo codes and soft‐decision decoded Bose‐Chaudhuri‐Hocquenghem (BCH) codes. The analysis considers relevant metrics like the codeword error rate, the frame error rate, and the undetected frame error rate. The considered codes include binary and non‐binary low‐density parity‐check codes, parallel turbo codes and extended BCH codes, with different decoding algorithms. The complexity of the various schemes and possible limits for their application are considered and discussed. Several numerical examples are provided. International Journal of Satellite Communications and Networking. Copyright © 2014 John Wiley & Sons, Ltd.     

多通道NAND闪存控制器的硬件实现

本文提出了在一款片上系统(SOC)芯片设计中的多通道NAND闪存控制器实现方案。在对NAND闪存控制器的结构和实现方法的研究上,闪存控制器利用带两个16K字节缓冲器的高效率缓冲管理控制器来管理4个通道,每个通道可以连接4片闪存芯片。控制器内嵌16比特BCH纠错模块,支持AMBAAHB总线与MLC闪存。文中还介绍了行地址计算与快闪存储器存储单元的初始化。结果分析里给出了控制器的仿真波形、功耗分析和综合结果。在一个存储组与一个通道的配置条件下,控制器的实现只需要71K逻辑门。     

二进制BCH码的一种盲识别方法

提出二进制BCH码的一种盲识别方法。该算法适用于本原和非本原二进制BCH码。首先,在帧长度已知的条件下,根据循环特性,给出一种分组长度的统计识别方法;然后,根据循环特性及各种约束条件得到备选多项式;再根据校正子权重和最小原则,得到最优多项式;最后通过因式分解得到生成多项式的最终估计表达式。仿真表明,本文算法具有较强的抗随机误码能力,而且其识别性能随着参加统计的码字数增多而提高。该算法不涉及矩阵运算,因此非常适合硬件实现。     

Low complexity distributed video coding

ContextConventional video encoding is a computationally intensive process that requires a lot of computing resources, power and memory. Such codecs cannot be deployed in remote sensors that are constrained in terms of power, memory and computational capabilities. For such applications, distributed video coding might hold the answer.ObjectiveIn this paper, we propose a distributed video coding (DVC) architecture that adheres to the principles of DVC by shifting the computational complexity from the encoder to the decoder and caters to low-motion scenarios like video conferencing and surveillance of hallways and buildings.MethodThe architecture presented is block-based and introduces a simple yet effective classification scheme that aims at maximizing the use of skip blocks to exploit temporal correlation between consecutive frames. In addition to the skip blocks, a dynamic GOP size control algorithm is proposed that instantaneously alters the GOP size in response to the video statistics without causing any latency and without the need to buffer additional frames at the encoder. To facilitate real-time video delivery and consumption, iterative channel codes like low density parity check codes and turbo codes are not used and in their place a Bose–Chaudhuri–Hocquenghem (BCH) code with encoder rate control is used.ResultsIn spite of reducing the complexity and eliminating the feedback channel, the proposed architecture can match and even surpass the performance of current DVC systems making it a viable solution as a codec for low-motion scenarios.ConclusionWe conclude that the proposed architecture is a suitable solution for applications that require real-time, low bit rate video transmission but have constrained resources and cannot support the complex conventional video encoding solutions.Practical implicationsThe practical implications of the proposed DVC architecture include deployment in remote video sensors like hallway and building surveillance, video conferencing, video sensors that are deployed in remote regions (wildlife surveillance applications), and capsule endoscopy.     

POCSAG码的接收与软件译码方法

研究了POCSAG码的接收和软件译码方法，描述了POCSAG码信号的获取方案，基于单片机实现了位同步和码字的校验与纠错，给出了码字中信息提取的实例。     

Long Binary Narrow-Sense BCH Codes Are Normal

Let C be the binary narrow-sense BCH code of length where m is the order of 2 modulo n. Using characters of finite fields and a theorem of Weil, and results of Vladut-Skorobogatov and Lang-Weil we prove that the code C is normal in the non-primitive case if and in the primitive case if where the constant depends only on t. Received January 4, 1994     

The effect of channel errors on the performance of a contention-based tdma protocol

A previously proposed contention-based TDMA protocol is modified to remain operational for a channel which is not noise free. The protocol is a mixture of random accessing and time division multiplexing and is suitable for data transmission through a channel which is characterized by non-negligible round-trip signal propagation delay. The effect of channel errors on the performance of the protocol is studied. Through numerical calculation it is observed that for the bit-error-rates encountered in practice the protocol remains stable. When the channel becomes rather noisy, error correcting codes can be imbedded to improve the performance. The validity of analysis has been verified by computer simulation.     

应用于片上网络的BCH码的设计与实现

本文对差错控制编码技术在片上网络(NoC)中的应用进行了研究。通过对三种纠错码在纠错能力、码率、面积和功耗等方面的折中,本文设计实现了适用于片上网络通信的BCH码,并给出了仿真结果。最后将BCH码应用在Hermes NoC平台上,成功地实现了一个基于BCH码的交换—交换的NoC差错控制系统。