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排序方式: 共有626条查询结果,搜索用时 15 毫秒
1.
In a typical embedded CPU, large on-chip storage is critical to meet high performance requirements. However, the fast increasing size of the on-chip storage based on traditional SRAM cells makes the area cost and energy consumption unsustainable for future embedded applications. Replacing SRAM with DRAM on the CPU’s chip is generally considered not worthwhile because DRAM is not compatible with the common CMOS logic and requires additional processing steps beyond what is required for CMOS. However a special DRAM technology, Gain-Cell embedded-DRAM (GC-eDRAM) [1], [2], [3] is logic compatible and retains some of the good properties of DRAM (small and low power). In this paper we evaluate the performance of a novel hybrid cache memory where the data array, generally populated with SRAM cells, is replaced with GC-eDRAM cells while the tag array continues to use SRAM cells. Our evaluation of this cache demonstrates that, compared to the conventional SRAM-based designs, our novel architecture exhibits comparable performance with less energy consumption and smaller silicon area, enabling the sustainable on-chip storage scaling for future embedded CPUs. 相似文献
2.
Xu Baowen Zhang Weifeng 《电子科学学刊(英文版)》2002,19(4)
The users' interest can be mined from the web cache and can be used widely. The interest can be specialized by the two-tuple (term, weight) in the simple interest model, in which the association relations are not mined, and then the interest cannot be associated in expressing the users' interest. Based on analyzing the WWW cache model, this letter brings forward a two-dimensional interest model and gives the interrelated methods on how to store the two-dimensional interest model effectively. 相似文献
3.
XuBaowen ZhangWeifeng 《电子科学学刊(英文版)》2002,19(4):399-402
The users‘ interest can be mined from the web cache and can be used widely.The interest can be specialized by the two-tuple(term,weight) in the simple interest model,in which the association relations are not mined.and then interest cannot be associated in expressing the users‘interest.Based on analyzing the WWW cache model,this letter brings forward a twodimensional interest model and gives the interrelated methods on how to store the two-dimensional interest model effectively. 相似文献
4.
流媒体技术是宽带网应用的支撑技术,在宽带建设中应用是最关键的,文章从宽带网建设的困惑谈起,详细介绍了流媒体技术的原理、实现方法,最后谈到世界上3家主流公司流媒体产品的基本情况。 相似文献
5.
We propose a general modeling framework to evaluate the performance of cache consistency algorithms. In addition to the usual hit rate, we introduce the hit* rate as a consistency measure, which captures the fraction of non-stale downloads from the cache. We apply these ideas to the analysis of the fixed TTL consistency algorithm in the presence of network delays. The hit and hit* rates are evaluated when requests and updates are modeled by renewal processes. Classical results on the renewal function lead to various bounds. 相似文献
6.
改善磁盘阵列性能的方法 总被引:5,自引:0,他引:5
磁盘阵列是解决计算机I/O瓶颈问题的有效方法之一,通过对现有磁盘阵列结构的研究,提出了4种改善磁盘阵列性能的方法,即良分利用磁盘带宽,平衡多盘的负载,减少奇偶检验数据存取时间和磁盘阵列Cache技术等,分析结果表明:在事务处理应用领域,利用Cache来把小写转化为大写可大大改善目前一般情况下,以一道数据大小来作为磁盘的基本存取大小是合适的选择,磁盘阵列负载平衡设计不足是指正常模式下系统请求在多盘间 相似文献
7.
Sven Beyer Christian Jacobi Daniel Kröning Dirk Leinenbach Wolfgang J. Paul 《International Journal on Software Tools for Technology Transfer (STTT)》2006,8(4-5):411-430
In the verified architecture microprocessor (VAMP) project we have designed, functionally verified, and synthesized a processor
with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts, pipelined fully IEEE
compatible dual precision floating point unit with variable latency, and separate instruction and data caches. The verification
has been carried out in the theorem proving system PVS. The processor has been implemented on a Xilinx FPGA.
A shorter version of this article with the title “Instantiating uninterpreted functional units and memory system: functional
verification of the VAMP” appeared in [8]. The work reported here was done while all the authors were with Saarland University. 相似文献
8.
本文主要讲述如何利用Cache技术,来有效的提高网站性能。以ASP.NET为基础,展示ASP.NET中使用Cache的新特性,主要应用了Databasedependencies技术。 相似文献
9.
Eduardo H.M. Cruz Matthias Diener Marco A.Z. Alves Philippe O.A. Navaux 《Journal of Parallel and Distributed Computing》2014
In current computer architectures, the communication performance between threads varies depending on the memory hierarchy. This performance difference must be considered when mapping parallel applications to processor cores. In parallel applications based on the shared memory paradigm, the communication is difficult to detect because it is implicit. Furthermore, dynamic mapping introduces several challenges, since it needs to find a suitable mapping and migrate the threads with a low overhead during the execution of the application. We propose a mechanism to detect the communication pattern of shared memory applications by monitoring cache coherence protocols. We also propose heuristics that, combined with our communication detection mechanism, allow the mapping to be performed dynamically by the operating system. Experiments with the NAS Parallel Benchmarks showed a reduction of up to 13.9% of the execution time, 30.5% of the cache misses and 39.4% of the number of invalidation messages. 相似文献
10.