An initial evaluation of the Convex SPP-1000 for earth and space science applications

The Convex SPP-1000 is the most recent of the new generation of Scalable Parallel Computing systems being offered commercially. The SPP-1000 is distinguished by incorporating the first commercial version of directory based cache coherence mechanisms and the emerging Scalable Coherent Interface protocol to achieve a true global shared memory capability. Pairs of HP PA-RISC processors are combined in clusters of 8 processors using a cross-bar switch. Up to 16 clusters are interconnected using 4 ring networks in parallel with a distributed global cache. To evaluate this new system in a Beta test environment, the Goddard Space Flight Center conducted three classes of operational experiments with an emphasis on applications related to Earth and space science. A cluster was tested as a platform for executing a multiple program workload exploiting job-stream level parallelism. Synthetic programs were run to measure overhead costs of barrier, fork-join, and message passing synchronization primitives. A key problem for Earth and space science studies is gravitational N-body simulation of solar systems to galactic clusters. An efficient tree-code version of this problem was run to reveal scaling properties of the system and to measure the overall efficiency. This paper presents the experimental results and findings of this study and provides the earliest published evaluation of this new scalable architecture.     

Highly configurable platforms for embedded computing systems

Platform chips, which are pre-designed chips possessing numerous processors, memories, coprocessors, and field-programmable gates arrays, are becoming increasingly popular. Platforms eliminate the costs and risks associated with creating customized chips, but with the drawbacks of poorer performance and energy consumption. Making platforms highly configurable, so they can be tuned to the particular applications that will execute on those platforms, can help reduce those drawbacks. We discuss the trends leading embedded system designers towards the use of platforms instead of customized chips. We discuss UCR research in designing highly configurable platforms, highlighting some of our work in highly configurable caches, and in hardware/software partitioning.     

一种 新的Cache优化方法—部分Cache局部性方法

Ｃａｃｈｅ的性能优化在高性能计算中起着非常重要的作用。传统的Ｃａｃｈｅ优化方法存在着一些缺陷。本文分析ＲＩＳＣ处理器的特点的基础 上，提出了“部分ｃａｃｈｅ方法。实践表明，该方法有很好的优化效果，且易实于实现。     

Winter is here! A decade of cache-based side-channel attacks,detection & mitigation for RSA

Timing-based side-channels play an important role in exposing the state of a process execution on underlying hardware by revealing information about timing and access patterns. Side-channel attacks (SCAs) are powerful cryptanalysis techniques that focus on the underlying implementation of cryptographic ciphers during execution rather than attacking the structure of cryptographic functions. This paper reviews cache-based software side-channel attacks, mitigation and detection techniques that target various cryptosystems, particularly RSA, proposed over the last decade (2007–2018). It provides a detailed taxonomy of attacks on RSA cryptosystems and discusses their strengths and weaknesses while attacking different algorithmic implementations of RSA. A threat model is presented based on the cache features that are being leveraged for such attacks across cache hierarchy in computing architectures. The paper also provides a classification of these attacks based on the source of information leakage. It then undertakes a qualitative analysis of secret key retrieval efficiency, complexity, and the features being exploited on target cryptosystems in these attacks. The paper also discusses the mitigation and detection techniques proposed against such attacks and classifies them based on their effectiveness at various levels in caching hardware and leveraged features. Finally, the paper discusses recent trends in attacks, the challenges involved in their mitigation, and future research directions needed to deal with side-channel information leakage.     

HTML5混合式移动社交应用中缓存管理机制的研究

随着移动互联网的发展,混合式开发作为一种快速开发的方式已经成为一种趋势,这种方式既可以体现Web应用可以同时适用于IOS平台和Android平台的特点,又能解决Web应用中不能调用操作系统底层资源的问题。当今社交类应用中普遍存在大量的图片,重复图片从服务器多次存取会消耗客户端流量、增加访问延迟,当今混合式开发框架中的缓存机制并不能解决这个问题。因此提出一个可以适用于混合式移动社交应用的图片缓存管理机制,提供缓存图片管理的原生模块供开发者在混合模式下使用,并将其应用于社交应用中。同时提出了一种基于社交关系的图片缓存替换算法,该算法结合了社交应用中用户之间的社交关系亲密值、LRU算法、图片占用空间大小。实际应用表明,该算法可以提高混合式移动社交应用中的缓存命中率。     

基于SDN的无线网状网络缓存位置决策和操作分配方案

针对信息中心网络缓存管理效率较低的问题,提出一种旨在提高缓存管理效率的方法,且充分利用了无线网状网络(WMN)环境中软件定义网络(SDN)的概念。主要工作体现在SDN内容管理上,缓存位置决策考虑了网络拓扑位置、内容尺寸和缓存节点资源的位置。缓存操作考虑了请求客户端和缓存节点位置,且操作分为通过分支点的off-path缓存和通过缓存节点内容流的on-path缓存。控制器通过缓存内容表来确定工作的分配。实验在两种环境下进行:含有局部聚合客户端的小型网络和局部分布式客户端的大型网络。结果显示,所提方案仅利用每秒5.13kb的控制流量负荷即可将随机缓存位置方案的平均响应延迟减少23.95%。相比于其他网络缓存方案,所提方案最大化了WMN的节点缓存效率,明显提升了内容缓存分配性能,且系统没有较大的额外开销。     

一种基于社交关系的移动缓存替换算法

近年来移动互联网尤其是Android平台和iOS平台的兴起,移动应用的数量出现了爆炸式增长。这些移动应用中,用户可以发布数据或浏览其他用户发布的数据,由此产生了大量用户生成的数据。当手机使用者想要浏览这些由其他用户生成的数据时,每次都向服务器请求数据的做法是不可取的,比较合适的方法是使用缓存技术将部分数据缓存在移动端,以此来降低数据的请求频率,减小无线网络带宽压力,提升用户体验。传统的缓存技术更多关注的是缓存的访问频率、最近访问时间等因素,但是很少关注数据生成用户之间的社交关系。在存在用户关系的移动网络中,用户相关数据的请求与用户之间的社交关系紧密联系。结合用户之间的社交关系、最近最久访问时间以及缓存中每块数据的大小,提出了一种基于社交关系的移动缓存替换算法。该算法综合计算数据的最近最久访问时间、数据产生用户与使用者之间的亲密值以及缓存占用存储空间的大小,在需要时进行缓存替换。实验证明在移动社交网络中,基于社交关系的缓存替换策略可以提高缓存命中率,使用户获得更好的体验。     

面向多线程应用的片上多核处理器私有LLC优化

片上多核处理器已逐渐取代传统超标量处理器成为集成电路设计的主流结构,但芯片的存储墙问题依旧是设计的一个难题。CMP通过大容量的末级高速缓存来缓解访存压力。在软件编程模式向多线程并行方式转变的背景下,针对多线程应用在多核处理器上的Cache访问特征,提出一种面向私有末级Cache的优化算法,通过硬件缓冲器记录处理器访存地址,从而实现共享数据在Cache间的传递机制,有效降低Cache失效开销。实验结果表明,在硬件开销不超过Cache部件0.1%的情况下,测试用例平均加速比为1.13。     

WARP: Memory Subsystem Effective for Wrapping Bursts of a Cache

State‐of‐the‐art processors require increasingly complicated memory services for high performance and low power consumption. In particular, they request transfers within a burst in a wrap‐around order to minimize the miss penalty of a cache. However, synchronous dynamic random access memories (SDRAMs) do not always generate transfers in the wrap‐round order required by the processors. Thus, a memory subsystem rearranges the SDRAM transfers in the wrap‐around order, but the rearrangement process may increase memory latency and waste the bandwidth of on‐chip interconnects. In this paper, we present a memory subsystem that is effective for the wrapping bursts of a cache. The proposed memory subsystem makes SDRAMs generate transfers in an intermediate order, where the transfers are rearranged in the wrap‐around order with minimal penalties. Then, the transfers are delivered with priority, depending on the program locality in space. Experimental results showed that the proposed memory subsystem minimizes the memory performance loss resulting from wrapping bursts and, thus, improves program execution time.     

面向云应用的存储缓存子系统

性能是云应用的重要指标,云应用与现有应用在数据存储与管理方式和访问模式等方面存在较大差异,这使得传统的缓存管理算法难以适应云应用的要求。针对云应用的特性,设计了基于影响因子的缓存策略,亦即将元数据和数据缓存分开管理,使用影响因子综合管理影响缓存被再次访问的几率的多种因素,区别创建、打开、读取和修改等操作对缓存再次访问的几率的影响;设计了缓存关联管理策略,即利用元数据和数据之间的关联提高缓存管理的性能;设计了缓存主动调度策略,即通过主动淘汰较低影响因子的缓存项和动态调整元数据与数据缓存的大小来提高缓存子系统的适应能力和性能。最后实现了原型系统,并使用Filebench和Postmark进行了测试和分析,验证了面向云应用缓存子系统原型能提高1%~120%的I/O性能以及2%~87%的操作处理速度。