Address independent estimation of the boundaries of cache performance

Worst-case (WCET) and best-case (BCET) execution times must be estimated in real-time systems. Worst-case memory performance (WCMP) and best-case memory performance (BCMP) components are essential to estimate them. These components are difficult to calculate in the presence of data caches, since the data cache performance depends largely on the sequence of memory addresses accessed. These addresses may be unknown because the base address of a data structure is unavailable for the analysis or it may change between different executions. This paper introduces a model that provides fast and tight valid estimations of the BCMP, despite ignoring the base address of the data structures. The model presented here, in conjunction with an existing model that estimates the WCMP, can provide base-address independent estimations of the BCMP and WCMP. The experimental results show that the base addresses of the data structures have a large influence in the cache performance, and that the model estimations of the boundaries of the memory performance are valid for any base addresses of the data structures.     

Study of the performance impact of a cache buffer in solid-state disks

An SSD generally has a small memory, called cache buffer, to increase its performance and the frequently accessed data are maintained in this cache buffer. These cached data must periodically write back to the NAND Flash memory to prevent the data loss due to sudden power-off, and it should immediately flush all dirty data items into a non-volatile storage media (i.e., NAND Flash memory), when receiving a flush command, while the flush command is supported in Serial ATA (SATA) and Serial Attached SCSI (SAS). Thus, a flush command is an important factor to give significant impact on SSD performance.In this paper, we have investigated the impact of a flush command on SSD performance and have conducted in-depth experiments with versatile workloads, using the modified FlashSim simulator. Our performance measurements using PC and server workloads provide several interesting conclusions. First, a cache buffer without a flush command could improve SSD performance as a cache buffer size increases, since more requested data could be handled in the cache buffer. Second, our experiments have revealed that a flush command might give a negative impact on SSD performance. The average response time per request with a flush command is getting worse compared to not supporting the flush command, as cache buffer size increases. Finally, we have proposed the backend flushing scheme to nullify the negative performance impact of the flush command. The backend flushing scheme first writes the requested data into a cache buffer and sends the acknowledgment of the request completion to a host system. Then, it writes back the data in the cache buffer to NAND Flash memory. Thus, the proposed scheme could improve SSD performance since it might reduce the number of the dirty data items in a cache buffer to write back to NAND Flash memory.All these results suggest that a flush command could give a negative impact on SSD performance and our proposed backend flushing scheme could improve the SSD performance while supporting a flush command.     

Efficient cache invalidation schemes for mobile data accesses

This paper presents two cache invalidation schemes to maintain data consistency between the server and clients in a mobile environment. Designed according to real situations like MANET, the Adaptive Data Dividing (ADD) scheme divides data into groups of different utilization ratios and varies group broadcast intervals to reduce data access time and bandwidth consumption. The Data Validity Defining (DVD) scheme aims to solve the validity problem of cached data items, which usually happens after clients disconnect from the server. Experimental evaluations and performance analyses exhibit that the two schemes outperform most existing cache invalidation schemes in terms of data access time, cache miss ratios, query uplink ratios and bandwidth consumption.     

多级缓存模式下的数据块替换优化算法

多数处理器中采用多级包含的cache存储层次,现有的末级cache块替换算法带来的性能开销较大.针对该问题,提出一种优化的末级cache块替换算法PLI,在选择丢弃块时考虑其在上级cache的访问频率,以较小的代价选出最优的LLC替换块.在时钟精确模拟器上的评测结果表明,该算法较原算法性能平均提升7％.     

基于分级Cache的透明计算系统

设计并实现一个基于分级Cache的透明计算系统HCTS,在系统客户端和服务端采用两级缓存来提升I/O性能。在缓存的管理策略上,针对透明计算应用环境,以提高缓存命中率为主要目标,提出一种基于访问频率计数阈值的改进LRU置换算法LRU-AFS。测试结果表明,当网络环境中的客户主机数不断增加时,与普通透明计算系统TS相比,HCTS能够在减少网络流量的同时大幅缩短客户机启动时间,提高随机读写吞吐量。     

一种新型共享Cache动态划分机制

综合效用最优划分共享Cache方法和传统LRU方法的优点,提出一种新的动态划分共享Cache方法。该方法可消除不同线程在共享Cache中的相互影响,当多核并行执行的程序均对共享Cache中占有的路数敏感时,可解决采用效用最优划分方法时的性能下降问题。经SPEC CPU2000测试表明,该方法与传统LRU和效用最优划分方法相比,系统整体性能平均分别提高20.28%和14.37%。     

一种面向SaaS应用多级定制模型的缓存技术研究

对共享架构共享存储的SaaS应用来说,如何实现SaaS应用数据低代价高速查询一直是其中的焦点问题之一.在元数据驱动的SaaS应用多级定制模型中,定制元数据存在层次关系,查询代价较高,普通的数据查询优化机制不足以实现SaaS应用的性能优势.采用元数据传递闭包策略解决该问题,针对多级定制的SaaS应用的特点,提出面向租户的...     

非结构化P2P网络的资源搜索算法研究

针对非结构P2P网络利用泛洪搜索机制进行资源搜索存在的问题,提出一种利用节点兴趣建立快捷链接,同时结合缓存技术的ICS搜索算法.实验结果表明,该算法不仅提高了搜索效率,也减少了网络流通的信息量.     

基于网络光盘库的Cache替换算法

Cache作为提高访问效率、改善系统性能的重要环节和技术，广泛地应用于各种计算、匹配场合中。除了在处理器上使用之外，在Web访问及存储系统中，为了提高访问速度，Cache也扮演了重要的角色。该文分析了当前应用于处理器、Web Cache等方面的替换算法，针对网络光盘库这个存储系统的自身特点，提出了一种新的替换算法。该算法结合了LFU和MQ这两种算法的特点，提高了数据在Cache中的命中率。实验表明替换算法与访问模型密切相关。     

基于AES算法的Cache Hit旁路攻击

AES加密快速实现中利用了查表操作,查表的索引值会影响Cache命中率和加密时间,而查表的索引值和密钥存在密切关系。通过分析AES最后一轮加密过程中查表索引值与密文和最后一轮子密钥的关系,以及它们对Cache命中与否和加密时间长短的影响,提出一种利用Cache hit信息作为旁路信息对AES进行旁路攻击的技术,在Intel Celeron 1.99 GHz和Pentium4 3.6 GHz CPU的环境中,分别在221和225个随机明文样本的条件下,在5 min内恢复了OpenSSL v.0.9.8(a)库中AES的128 bit密钥,并介绍防御这种攻击途径的手段。