基于B/S/S架构的高校教务管理系统的应用与研究

文章的研究来源于广西某师范成教学院的教务管理系统,针对成教学院的教务管理工作强度高、效率低等特点,系统采用B/S/S架构,运用了分页、数据库连接池、内存缓存等技术,开发的教务管理系统满足了用户的需求,具有很大的实用性和推广性.     

非结构化P2P网络的资源搜索算法研究

针对非结构P2P网络利用泛洪搜索机制进行资源搜索存在的问题,提出一种利用节点兴趣建立快捷链接,同时结合缓存技术的ICS搜索算法.实验结果表明,该算法不仅提高了搜索效率,也减少了网络流通的信息量.     

优化机器人多处理机控制系统性能方法

分析了有腿的步行机器人控制器性能瓶颈的产生原因.提出优化机器人多处理机控制系统性能的有效方法。     

乱序执行机器上的load指令调度

随着处理器和存储器速度差距的不断拉大，访存指令尤其是频繁cache miss的指令成为影响性能的重要瓶颈。编译器由于无法得知访存指令动态执行的拍数，一般假定这些指令的延迟为cache命中或者cache miss的延迟，所以并不准确。我们引入cache profiling技术来收集访存指令运行时的cache miss或者命中的信息，利用这些信息来计算访存的延迟。乱序机器上硬件的指令调度对于发射窗口内的指令能进行很好的动态调度，编译器则对更长的范围内的指令调度更有优势。在reorder buffer中cache miss一旦发生，容易引起reorder buffer满，导致流水线阻塞。调度容易cache miss的指令。使其并行执行，从而隐藏cache miss的长延迟，就可以提高程序性能。因此，我们针对load指令，一方面修改频繁miss的指令的延迟，一方面修改调度策略，提高存储级并行度。实验证明，我们的调度对于bzip2有高达4．8％的提升，art有4％的提升，整体平均提高1．5％。     

一种高效的指令缓存单元架构及其性能分析

为了提高高速DSP或通用处理器的程序执行速度,描述了一种指令缓存单元的有效架构,特别是实现细节和性能分析.因所提出的指令缓存单元是为一种高性能VLIW结构的DSP核而设计,使用了并行的标签比较逻辑和寄存器堆的结构,芯片面积、关键路径延迟、功耗都大大减小.该指令缓存单元使用高层次的RTL(使用Verilog)编码,并由Synopsys的Design Compiler综合,使用不同的StarCoreTM基准程序测试比较,并进行性能分析.比较结果表明,所提出的结构是有效的,适合用于任何高速的处理器核.     

动态可重构高速缓存结构的研究与设计

提出了一种动态可重构高速缓存结构,提升了系统性能;同时,大大降低了功耗。该结构在传统高速缓存上作少量的硬件改动,实现了高速缓存容量、块大小和关联度的动态可配置性。实验结果表明,相对于传统结构,动态可重构高速缓冲存储器在不损失性能的前提下,取得了很好的降低系统功耗的效果。     

DIG: Degree of inter-reference gap for a dynamic buffer cache management

The effectiveness of the buffer cache replacement is critical to the performance of I/O systems. In this paper, we propose a degree of inter-reference gap (DIG) based block replacement scheme. This scheme keeps the simplicity of the least recently used (LRU) scheme and does not depend on the detection of access regularities. The proposed scheme is based on the low inter-reference recency set (LIRS) scheme, which is currently known to be very effective. However, the proposed scheme employs several history information items whereas the LIRS scheme uses only one history information item. The overhead of the proposed scheme is almost negligible. To evaluate the performance of the proposed scheme, the comprehensive trace-driven computer simulation is used in general access patterns. Our simulation results show that the cache hit ratio (CHR) in the proposed scheme is improved as much as 65.3% (with an average of 26.6%) compared to the LRU for the same workloads, and up to 6% compared to the LIRS in multi3 trace.     

Optimization of I/O systems by cache disks and file migration: A summary

The file system, and the components of the computer system associated with it (disks, drums, channels, mass storage tapes and tape drives, controllers, I/O drivers, etc.) comprise a very substantial fraction of most computer systems; substantial in several aspects, including amount of operating system code, expense for components, physical size and effect on performance. In a comparison paper, we surveyed the traditional methods for optimizing the I/O system. We then examined disk and I/O system architecture in IBM type systems, and indicated shortcomings and future directions. In this paper we go one step further and summarize research by the author on two topics: cache disks and file migration. Cache disks are disks which have an associated cache which buffers recently used tracks of data. The case for cache disks is presented, and some of the issues are discussed. Parameter values for some aspects of the cache design are suggested. The second part of this paper summarizes the author's work on file migration, by which files are migrated between disk and mass storage as needed in order to effectively maintain on-line a much larger amount of information than the disks can hold. Some of the algorithms investigated are discussed, and the basic results are presented.     

基于缓存和实时压缩的动态Web内容加速机制研究

当前的Web缓存机制不能有效地处理越来越多的动态内容。本文结合代理缓存和HTTP实时压缩机制．引入规则处理集，在缓存静态内容的基础上，动态协商Web动态响应内容的压缩和缓存，提高缓存命中率，减少传输内容的长度，从而减缓Web服务器的负载，增加系统吞吐量。理论分析和性能测试表明该方法能有效地实现动态内容加速。     

基于OPT Cache替换Profiling的Cache提示生成

提出了一个基于最优Cache替换（OPT）Profiling的静态Cache提示生成方法,并通过模拟SPEC2000Int测试程序,对该方法与LRU Cache替换策略进行了性能比较。