流媒体服务中基于分布式代理的缓存数据放置策略

随着高速宽带接入技术的发展,流媒体技术的研究得到了迅速的发展,并具有广阔的应用前景.流媒体代理技术作为减轻服务器的访问负载、提高用户的访问响应速度的重要手段,已成为流媒体研究领域中的研究热点之一.针对流媒体服务中的分布式代理服务器系统,提出了一种优化的缓存数据放置策略.其主要思想是将缓存数据放入某个特定的代理服务器中,使得今后访问该数据的网络传输开销最小.仿真实验表明,所提出的算法比传统的缓存数据放置算法能获得更小的传输开销和更好的可扩展性.     

PowerPC计算机系统级速度影响因素的研究

PowerPC处理器是目前使用最广泛的RISC处理器,设计基于PowerPC处理器高性能计算机的要求十分迫切。计算机系统结构中影响系统级速度的最主要因素为Cache状态、硬件等待数、编译系统以及操作系统。通过在基于PowerPC处理器的被测系统上使用典型算例,针对以上四个因素进行测试和研究,得到了硬件等待数、Cache状态、编译系统以及操作系统对系统级速度影响的数据,并给出测试结论和系统架构的设计建议。     

基于“嵩山”超级计算机系统的大规模管网仿真

供水管网仿真广泛应用于城市供水输配调度,是城市供水管网监测与维护的重要技术手段。由于在面向城市级的大规模管网中产生了海量的计算数据,因此在一般计算平台上无法满足管网仿真计算的算力需求。为提升城市级供水管网仿真的计算效率,提出一种有效的并行化方案。基于“嵩山”超级计算机系统采用中央处理器+数据缓存单元（CPU+DCU）架构,利用其在密集数据计算方面的优势,对“嵩山”超级计算机进行供水管网仿真。参照可移植性异构计算接口（HIP）异构编程模型,在“嵩山”超级计算机上实现供水管网仿真的异构计算,并结合管道数据分割方案,使用消息传递接口开启多进程以实现DCU加速数据通信传递。通过重定义数据类型解决计算过程中结构体传输问题,实现单节点内多DCU的大规模密集计算。在不同计算平台和多种计算策略仿真上的对比结果表明,与传统x86平台相比,该优化方案在小规模数据与大规模数据上的加速比分别达到5.269、10.760,与采用计算统一设备架构异构编程模型的传统GPU异构平台相比,计算性能有明显提高。     

基于区域协作的Cache压缩

为提高Cache的有效容量,进行了Cache压缩研究,并提出了一种区域协作压缩(RCC)方法,以提升最后一级缓存的压缩率。与传统的Cache压缩算法不同,RCC方法利用了缓存区域的压缩局部性,使用缓存区域中第一个缓存块的字典信息来协作压缩缓存区域中的其他各个缓存块,而不需要对缓存区域进行整体压缩。RCC有效发掘了缓存区域内缓存块之间的数据冗余,实现了接近以缓存区域为压缩粒度的字典压缩的压缩率,然而压缩、解压缩延时却仍然和压缩单个缓存块时相当。实验结果表明,与单缓存块压缩算法C-PACK相比,RCC方法的压缩率平均提升了12.34%,系统的性能提升了5%。与2倍容量的非压缩Cache相比,有效容量提升了27%,系统性能提升了8.6%,而面积却减少了63.1%。     

一种Cache一致性协议验证中覆盖率驱动的随机验证方法

随机验证技术是当今大规模集成电路仿真验证流程中的一项重要支撑技术,覆盖率驱动的随机测试生成方法是目前该领域研究的热点之一。针对Cache一致性协议的验证目标,介绍一种引入基于朴素贝叶斯模型的机器学习来完善基于覆盖率驱动的随机验证的方法,并结合相关的实际验证过程对该方法进行了分析和讨论。     

A structured P2P network based on the small world phenomenon

In this paper, we propose a new structured P2P overlay network, named SW-Uinta(small-world). In order to reduce the routing latency, we firstly construct the Uinta network in which both physical characteristics of network and data semantic are considered. Furthermore, based on Uinta, a nondeterministic caching strategy is employed to allow for poly-logarithmic search time while having only a constant cache size. Compared with the deterministic caching strategy proposed by previous P2P systems, the nondeterministic caching strategy can reduce communication overhead for maintaining the routing cache table. Cache entries in the cache table of peer nodes can be updated by subsequent queries rather than only by running stabilization periodically. In the following, a novel cache replacement scheme, named the SW cache replacement scheme, is used to improve lookup performance, which has proved to satisfy the small-world principle. So we call this network SW-Uinta(small-world). After that, according to the theoretical analysis, it can be proved that SW-Uinta(small-world) can get O((log ² N)/k) search time with O(k) cache size. Lastly, the performance of SW-Uinta(small-world) is compared with those of other structured P2P networks such as Chord and Uinta. It shows that SW-Uinta(small-world) can achieve improved object lookup performance and reduce maintenance cost.

改进的基于目录的Cache一致性协议

介绍几种典型目录一致性协议并分析它们的优缺点。在综合全映射目录和有限目录优点的基础上,通过在存储器层上增加一个存储器高速缓存（Cache）层的方式,提出并讨论一种改进后的Cache一致性协议。该协议相对有限目录存储开销增加不多的情况下,提高了系统性能和可扩展性。     

基于缓存偏移量的P2P流媒体调度策略

现有P2P流媒体调度策略在确定数据块调度优先级时,未能综合考虑数据块稀缺度和紧迫度因素,导致了较差的播放连续度和启动延迟性能。提出的基于缓存偏移量的数据调度策略通过统计数据块在供求节点上的播放偏移量并对其加以处理,可有效懈决该问题,使播放连续度、启动延迟性能得到明显提高。     

论数字图书馆系统中WEB服务器性能优化的方法

由于在数字图书馆系统中流通着的大多是数字化的索引、文摘、全文、图像或音频视频等多媒体信息,对Web服务器性能有着较高的要求.结合实际工程的经验,从硬件实现手段(缓存服务器、均衡负载设备、Web双机镜像等)和软件实现手段(多层软件结构设计、应用部署等)等两个大方面论述如何提高Web服务器性能,以便使用户能够更快捷、高效、安全地使用数字图书馆应用系统.     

Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology

Radiation-induced soft error has become an emerging reliability threat to high performance microprocessor design. As the size of on chip cache memory steadily increased for the past decades, resilient techniques against soft errors in cache are becoming increasingly important for processor reliability. However, conventional soft error resilient techniques have significantly increased the access latency and energy consumption in cache memory, thereby resulting in undesirable performance and energy efficiency degradation. The emerging 3D integration technology provides an attractive advantage, as the 3D microarchitecture exhibits heterogeneous soft error resilient characteristics due to the shielding effect of die stacking. Moreover, the 3D shielding effect can offer several inner dies that are inherently invulnerable to soft error, as they are implicitly protected by the outer dies. To exploit the invulnerability benefit, we propose a soft error resilient 3D cache architecture, in which data blocks on the soft error invulnerable dies have no protection against soft error, therefore, access to the data block on the soft error invulnerable die incurs a considerably reduced access latency and energy. Furthermore, we propose to maximize the access on the soft error invulnerable dies by dynamically moving data blocks among different dies, thereby achieving further performance and energy efficiency improvement. Simulation results show that the proposed 3D cache architecture can reduce the power consumption by up to 65% for the L1 instruction cache, 60% for the L1 data cache and 20% for the L2 cache, respectively. In general, the overall IPC performance can be improved by 5% on average.