基于DSP的感应加热电源平台的研究

研究了将感应加热电源数字化技术整合后具有多项选择功能的感应加热电源研究平台,这是目前该领域研究的热点之一。该平台集成了Buck斩波、移相PWM两种调功方式以及PID、模糊控制算法,操作人员可根据不同情况选择不同的控制方案,提高了装置的自动化和智能水平。以TMS320F2812为核心,实现了外围检测调理电路、驱动电路、过流过压保护等。该实验平台减少了研究者的重复工作,可以提高研究效率,节省开发时间。     

On the power of clause-learning SAT solvers as resolution engines

In this work, we improve on existing results on the relationship between proof systems obtained from conflict-driven clause-learning SAT solvers and general resolution. Previous contributions such as those by Beame et al. (2004), Hertel et al. (2008), and Buss et al. (2008) demonstrated that variations on conflict-driven clause-learning SAT solvers corresponded to proof systems as powerful as general resolution. However, the models used in these studies required either an extra degree of non-determinism or a preprocessing step that is not utilized by state-of-the-art SAT solvers in practice. In this paper, we prove that conflict-driven clause-learning SAT solvers yield proof systems that indeed p-simulate general resolution without the need for any additional techniques. Moreover, we show that our result can be generalized to certain other practical variations of the solvers, which are based on different learning schemes and restart policies.     

Performance evaluation of the time delay digital tanlock loop architectures

This article presents the architectures, theoretical analyses and testing results of modified time delay digital tanlock loop (TDTLs) system. The modifications to the original TDTL architecture were introduced to overcome some of the limitations of the original TDTL and to enhance the overall performance of the particular systems. The limitations addressed in this article include the non-linearity of the phase detector, the restricted width of the locking range and the overall system acquisition speed. Each of the modified architectures was tested by subjecting the system to sudden positive and negative frequency steps and comparing its response with that of the original TDTL. In addition, the performance of all the architectures was evaluated under noise-free as well as noisy environments. The extensive simulation results using MATLAB/SIMULINK demonstrate that the new architectures overcome the limitations they addressed and the overall results confirmed significant improvements in performance compared to the conventional TDTL system.     

高速率8PSK信号的载波同步及实现

提出一种高速率8PSK信号的载波同步方案,数字锁相环组合频偏搜索实现接收机小频偏的载波同步;多组小频偏同步单元的并行操作获得接收机大频偏的粗略估计,基于反馈闭环实现载波粗同步,然后由一组小频偏同步单元完成残余频偏的精确跟踪及相位同步.分析了载波同步的抖动特性,并基于FPGA实现了该方案.测试结果表明,该载波同步方案动态范围大,跟踪性能好,相位抖动小,长期稳定性好,在中低信噪比下,系统实现损耗小于0.5dB.适合于中继卫星信道高速率8PSK信号的载波同步.     

基于DSP的全桥移相控制感应加热电源研究

设计了基于DSP的串联谐振式感应加热电源控制系统,以TMS520F2812为核心,实现了数字锁相环（DPLL）、移相PWM发生与功率闭环控制。实验验证了设计内容的正确性与可行性,从而提升了感应加热电源的数字化控制水平。     

基于DVI的时钟数据恢复电路设计

设计了一种实现DVI(digital visual interface)数字视频信号接收器的新型时钟数据恢复电路.通过在过采样电路和数字锁相环之间增加弹性缓冲电路,在实现10bit数据恢复的同时,使采样时钟频率减小为数据频率的2.5倍,DPLL同时对10bit并行的数据进行相位检测判断,提高了判断的正确率,使数据传输的误码率得到改善.采用SMIC0.18μm CMOS工艺流片,测试结果表明,输入三路并行的1.65Gbps/ch UXGA格式像素数据和传输电缆长度2m条件下,输出系统时钟信号最大抖动峰.峰值为183ps,均方值为24ps,满足DVI规范要求.     

一种感应加热电源的设计

感应加热电源在金属熔炼、铸造、锻造、透热、淬火、弯管、烧结、表面热处理、铜焊以及晶体生长等行业得到了广泛的应用。同时,由于感应加热电源的加热特点,超音频、大功率是感应加热电源领域研究的重点之一。详细介绍了所设计的感应加热电源,给出了实现的方法和实验电路,并对此方法进行了仿真。实验和仿真结果表明该设计方案具有一定的可行性。     

对高频逆变电源中DPLL的分析与设计

采用基于DSP的数字锁相环(DPLL)对高频逆变电源输出频率进行实时控制,可实现逆变器工作频率对负载谐振频率的同步跟踪,确保逆变器开关器件工作在零电压零电流软开关(ZVZCS)状态,显著减小功率器件的开关损耗和提高装置效率。本文在给出DPLL控制的逆变电源拓扑结构的基础上,推出了适用于高频逆变电源的锁相环数学模型,在Z域中对二阶数字锁相环进行了稳定性分析和动态设计。在对锁相环Z域传递函数分析的基础上,得出二阶数字锁相环的稳定条件,并用MATLAB对其进行了仿真分析,最后进行了实验验证。仿真和实验结果表明,在Z域中对基于DSP的二阶数字锁相环的动态分析和设计是合理可行的,用此方法设计的电源具有良好的动态响应和抗扰性能。     

宽频带数字锁相环设计及基于FPGA的实现

简要介绍了一种在FPGA中实现全数字锁相环(DPLL)的原理与方法,重点介绍了采用可控模数分频器实现的数字锁相环中宽频带捕获的方法与实现过程。文中采用较为简单的方法实现了捕获时间小而捕获带宽又相当宽的全数字锁相环,解决了“捕获时间”和“捕获带宽”指标相互矛盾的问题。可直接用于同步串行通信中二进制码流的同步时钟的恢复,且可自动跟踪接收码流速率的变换。该设计是基于FPGA的模块化设计,便于其他数字系统设计及通信系统的移植和集成。     

基于数字式锁相环的双向差动相位解调法设计

设计了应用于高精度干涉测量系统的双向差动相位解调法,利用锁相环的分频特性对测量信号进行降频处理,增加计数脉冲的数量,再结合双向差动相位解调法对信号进行鉴相,从而提高测量分辨力.在He-Ne双频激光外差偏振干涉信号处理实验装置中进行了实验,证明了该方法能够提高测量精度.