应用VHDL语言的FFT算法实现

针对目前数字信号处理中大量采用的FFT算法都需要软件来处理的问题，基于FFT算法的原理，采用硬件描述语言(VHDL)和现场可编程逻辑门阵列(FPGA)，建立了算法逻辑的硬件模型，并编程实现其逻辑运算功能，完成了FFT算法的硬件描述，经测试表明，数字信号的处理速度提高了10％～20％，特别适用于复杂信号的频谱分析，增强了数据处理的可靠性和稳定性。     

The Temperature Intelligence Control System Based on Single Chip-Microprocessor

The paper introduces a temperature control system based on AT89C51 single-chip-microprocessor, and discusses the principle , hardware structure, and software design of this system in detail.     

基于单片机的脉冲信号采集与处理

为了提高脉冲信号采集与处理的精度，从硬件、软件、采集与处理方法三个方面，探讨了采用单片机技术采集与处理三种脉冲信号的技术途径。设计了以主机板为核心配以三块接口板的硬件子系统和采用模块化分区结构的软件子系统。提出了显示功能子程序、加源刻度子程序、测井子程序的编制技术，以及三种脉冲信号采集与处理的方法。     

嵌入式Linux硬实时性的研究与实现

着重论述了增强嵌入式Linux实时性的基本策略，在实际项目中提出并实现了在实时硬件抽象层(RTHAL)的架构下，应用双内核机制使嵌入式Linux支持硬实时性的一种新的方案。     

Automatic Design of Application Specific Instruction Set Extensions Through Dataflow Graph Exploration

General-purpose processors are often incapable of achieving the challenging cost, performance, and power demands of high-performance applications. To meet these demands, most systems employ a number of hardware accelerators to off-load the computationally demanding portions of the application. As an alternative to this strategy, we examine customizing the computation capabilities of a processor for a particular application. The processor is extended with hardware in the form of a set of custom function units and instruction set extensions. To effectively identify opportunities for creating custom hardware, a dataflow graph design space exploration engine heuristically identifies candidate computation subgraphs without artificially constraining their size or shape. The engine combines estimates of performance gain, cost, and inherent limitations of the processor to grow candidate graphs in profitable directions while pruning unprofitable paths. This paper describes the dataflow graph exploration engine and evaluates its effectiveness across a set of embedded applications.     

Context Switching in a Run-Time Reconfigurable System

A distinguishing feature of reconfigurable computing over rapid prototyping is its ability to configure the computational fabric on-line while an application is running. Conventional reconfigurable computing platforms utilize commodity FPGAs, which typically have relatively long configuration times. Shrinking the configuration time down to the nanosecond region opens possibilities for rapid context switching and virtualizing the computational resources. An experimental context-switching FPGA, called the CSRC, has been created by BAE Systems, and gives researchers the opportunity to explore context-switching applications. This paper presents results obtained from constructing both control-driven and data-driven context switching applications on the CSRC device, along with unique properties of the run-time and compile-time environment.     

软硬件协同设计方法的研究

论述了嵌入式系统软硬件协同设计的一般方法，结合CORSAIR、COOL和POLIS 3种有代表性的软硬件协同设计系统，对系统描述、软硬件划分、软硬件协同综合等几个主要设计步骤进行了研究与分析，并提出了新的思路和方法。     

新型电能质量监测系统的设计

本文设计了一个用于低压配电系统的新型电能质量监测系统。该系统的设计包含现场设备、设备的操作系统以及数据发布系统三部分。基于双CPU设计的现场设备保证了系统的实时工作能力;采用嵌入式实时多任务操作系统作为现场设备的操作系统,不仅能提高其工作稳定性和功能扩展能力,还从根本上改变了以往硬件系统的软件设计过程。基于Web技术的数据发布系统提高了系统的数据处理和发布能力;由于该系统采用IEEE标准构建数据格式,其数据兼容性较好,而且扩展能力较强。     

基于DSP控制的电压调节器的研制

介绍一种基于数字信号处理单片机(TMS320F240)构成的谐波励磁同步发电机电压调节器，它具有硬件电路简单、性能价格比高、可靠性好等特点。     

BOAR: an advanced HW/SW coemulation environment for DSP system development

The BOAR emulation system is targeted to hardware/software (HW/SW) codevelopment of advanced embedded DSP and telecom systems. The challenge of the BOAR system is efficient customization of programmable hardware, and dedicated partitioning routine to target applications and structures, which allows quite high overall system performance. The system allows multiple configurations for communication between processors and field programmable gate arrays (FPGAs) making the BOAR system an efficient tool for real-time HW/SW coverification. The reprogrammable hardware of the emulation tool is based on four Xilinx 4000-series devices, two Texas TMS320C50 signal processors and one Motorola MC68302 microcontroller. With current devices the BOAR hardware provides approximately 40–70 kgates of logic capacity in DSP applications. The emulation capacity can be expanded by connecting several similar boards in chain. The system has also a versatile internal reprogrammable test environment for test bench development, performance evaluations and design debugging. The logic development environment is based on the Synopsys synthesis tools and an automatic design management software, which performs resource mapping and performance-driven design partitioning between FPGAs. The emulation hardware is currently connected to logic and software development environments via an RS-232C bus. The BOAR emulation system has been found a very efficient platform for real-life prototyping of different types of DSP algorithms and systems, and validating correct functionality of a VHDL macro library.