自动提取RTL级集成电路时序信息

文章以Verilog硬件描述语言描述的电路为研究对象，给出RTL级集成电路的静态时序深度和动态时序深度概念。从静态、动态两方面出发度量语句的执行效果和程序运行的时序关系，并实现了信息的自动提取，从而为高层次测试生成、设计验证提供了方便。     

四位微控制器电路的硬件结构和指令系统

本文较为详细的剖析了一种四位微控制器,给出了该微控制器的硬件结构与指令系统,为微控制器设计开发和推广应用提供了一种参考和技术支撑。     

现代电子设计工具与IP核的重用

简单介绍了硬件描述语言（HDL）和IP的概念;采用HDL和IP设计方法的优点;综述了目前世界上著名的ESDA厂商的前端设计工具;推广IP设计方法中的几个重要问题;以及由此对复杂数字电路系统设计和EDA工具发展产生的影响。对我国怎样在有限的人力物力的条件下培养人才,逐步推广HDL和IP设计方法提出了建议。     

电回声消除的DSP实现方法

文中描述了电回声消除的TMS320LC54X实现。该算法基于LNLMS自适应滤波,利用芯片LMS指令同时完成预测滤波和权值更新,系数采用单精度。该算法适于任意回声轨迹长度,只需很少的MIPS即可消除长达64ms的回声轨迹,并且无需外接存储器,在一个芯片上（LC548／9）可实现多通道工作。     

A new hardware Trojan detection technique using deep convolutional neural network

The involvement of external vendors in semiconductor industries increases the chance of hardware Trojan (HT) insertion in different phases of the integrated circuit (IC) design. Recently, several partial reverse engineering (RE) based HT detection techniques are reported, which attempt to reduce the time and complexity involved in the full RE process by applying machine learning or image processing techniques in IC images. However, these techniques fail to extract the relevant image features, not robust to image variations, complicated, less generalizable, and possess a low detection rate. Therefore, to overcome the above limitations, this paper proposes a new partial RE based HT detection technique that detects Trojans from IC layout images using Deep Convolutional Neural Network (DCNN). The proposed DCNN model consists of stacking several convolutional and pooling layers. It layer-wise extracts and selects the most relevant and robust features automatically from the IC images and eliminates the need to apply the feature extraction algorithm separately. To prevent the over-training of the DCNN model, a new stopping condition method and two new metrics, namely Accuracy difference measure (ADM) and Loss difference measure (LDM), are proposed that halts the training only when the performance of our model genuinely drops. Further, to combat the issue of process variations and fabrication noise generated during the RE process, we include noisy images with varying parameters in the training process of the model. We also apply the data augmentation and regularization techniques in the model to address the issues of underfitting and overfitting. Experimental evaluation shows that the proposed technique provides 99% and 97.4% accuracy on Trust-Hub and synthetic ISCAS dataset, respectively, which is on-an-average 15.83% and 21.69% higher than the existing partial RE based techniques.     

Efficient architecture of variable size HEVC 2D-DCT for FPGA platforms

This study presents a design of two-dimensional (2D) discrete cosine transform (DCT) hardware architecture dedicated for High Efficiency Video Coding (HEVC) in field programmable gate array (FPGA) platforms. The proposed methodology efficiently proceeds 2D-DCT computation to fit internal components and characteristics of FPGA resources. A four-stage circuit architecture is developed to implement the proposed methodology. This architecture supports variable size of DCT computation, including 4 × 4, 8 × 8, 16 × 16, and 32 × 32. The proposed architecture has been implemented in System Verilog and synthesized in various FPGA platforms. Compared with existing related works in literature, this proposed architecture demonstrates significant advantages in hardware cost and performance improvement. The proposed architecture is able to sustain 4 K@30 fps ultra high definition (UHD) TV real-time encoding applications with a reduction of 31–64% in hardware cost.     

VLSI parallel shift sort algorithm and design

A hardware algorithm called the parallel shift sort (PSS) is presented. The PSS is a hardware adaption of sorting by insertion. The function of the PSS is verified using an invariant method. Since the PSS uses an array of identical cells of low complexity, it is well suited for VLSI implementation. Some of the more important details of an NMOS implementation on a 5.4×5.4 mm chip are shown. The chip which contains approximately 8000 transistors is designed with lambda rules using a 4 μm line width process. A microcomputer expansion card with an array of sorting chips is described logically. The card's sorting time is of order O(N), where N is the product of the number of chips in the array and the number of cells in each chip (16 for the described chip implementation). The card is also capable of sorting arbitrarily wide keys in time proportional to N × K where K is the number of words in the sorting key width.     

CAD tool for hardware software co-synthesis of heterogeneous multiple processor embedded architectures

Hardware software co-synthesis process intends to determine an optimal architecture for an embedded application specified by a task graph or a specification language. In this paper, we present a co-synthesis approach targeting MPSoCs and distributed memory multiprocessor architectures for high performance embedded applications. Our co-synthesis approach produces pipelined multiprocessor architectures consisting of heterogeneous processing elements connected by a point-to-point communication structure. The co-synthesis process consists of four distinct phases; processing element selection for addition to the system, pipelined task allocation, scheduling and a regular interconnection topology mapping. Initially, an irregular topology is generated that is mapped to a regular architecture. Our co-synthesis methodology performs system partitioning and produces an irregular topology multiprocessor system. It also generates an optimal (or sub-optimal) regular topology architecture after considering some of the well-known regular topologies like mesh, hypercube, tree, etc. The co-synthesis method is demonstrated by exploring embedded architectures for MPEG encoder and artificially generated application task graphs representing complex embedded systems.     

芯片级木马检测技术研究综述

集成电路在各个领域都具有极其重要的作用,但是在当今集成电路设计、制造、测试、封装各种环节相分离的产业模式下,用户所使用的芯片可能会被别有用心者植入硬件特洛伊木马电路,这给信息安全领域带来了严重威胁,芯片级硬件木马的检测技术已经成为了芯片安全研究领域的新热点。首先介绍了硬件木马的概念、危害以及分类方式;然后对硬件木马检测技术国内外有影响的研究成果进行了详细的总结和评述,着重阐述了目前比较有效的旁路分析方法,指出基于功耗指纹分析的硬件木马检测技术是当前最有前途的一种检测方法;最后简要总结了硬件木马的主动防御机制。     

多元LDPC译码器设计

在多元低密度奇偶校验码(NB-LDPC)的扩展最小和译码算法（EMS）中,由于消息向量的递归计算和校验/变量节点信息之间的迭代交换,导致译码器存在较大延迟。针对此问题本文提出了一种新型译码器结构,它优化了校验节点更新单步运算单元,根据前向后向算法规则,以3路单步运算单元完成校验节点更新,硬件资源消耗略有增加,但所需时钟周期约降为一般结构的1/3;并采用全并行运算的变量节点信息更新单元,无需利用前向后向算法将更新过程分解为多个单步运算,消除了变量节点更新的递归计算,且具有低复杂度低延时等优点,并在现场可编程门阵列(FPGA)Xilinx Virtex-4 (XC4VLX200)平台上对一个GF(16)域上(480,360)的准循环多元LDPC码进行了综合仿真。仿真结果证明,设计的译码器在较小资源消耗条件下能成倍提高吞吐量。